steveicarus / iverilogLinks
Icarus Verilog
☆3,203Updated this week
Alternatives and similar repositories for iverilog
Users that are interested in iverilog are comparing it to the libraries listed below
Sorting:
- Verilator open-source SystemVerilog simulator and lint system☆3,136Updated this week
- Yosys Open SYnthesis Suite☆4,088Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,732Updated last year
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆853Updated 4 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,897Updated last week
- cocotb: Python-based chip (RTL) verification☆2,117Updated last week
- A small, light weight, RISC CPU soft core☆1,468Updated 2 months ago
- RISC-V CPU Core (RV32IM)☆1,554Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,649Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,662Updated last month
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,421Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,646Updated last month
- nextpnr portable FPGA place and route tool☆1,532Updated last week
- VHDL 2008/93/87 simulator☆2,658Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,204Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,352Updated 2 weeks ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,987Updated 5 months ago
- SERV - The SErial RISC-V CPU☆1,661Updated last week
- Scala based HDL☆1,864Updated 2 weeks ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,153Updated this week
- Verilog library for ASIC and FPGA designers☆1,341Updated last year
- Rocket Chip Generator☆3,585Updated last month
- Spike, a RISC-V ISA Simulator☆2,867Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,130Updated 5 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,166Updated 2 years ago
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆827Updated 5 years ago
- The MyHDL development repository☆1,100Updated 6 months ago
- The Ultra-Low Power RISC-V Core☆1,628Updated 2 months ago
- 32-bit Superscalar RISC-V CPU☆1,106Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,010Updated 2 weeks ago