Alternatives and similar repositories for iverilog

Users that are interested in iverilog are comparing it to the libraries listed below

• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,016Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,054Updated last week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆830Updated 2 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,075Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,506Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,459Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,139Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,629Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,667Updated last year
• ghdl / ghdl
  VHDL 2008/93/87 simulator
  ☆2,627Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,157Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,847Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,639Updated 3 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,336Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,872Updated 2 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,628Updated 2 weeks ago
• myhdl / myhdl
  The MyHDL development repository
  ☆1,095Updated 5 months ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,543Updated last week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,339Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,611Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,969Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,117Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• nickg / nvc
  VHDL compiler and simulator
  ☆733Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,537Updated 3 years ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,405Updated last week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆789Updated last month
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,403Updated last month
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,092Updated 3 months ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆974Updated last year