Icarus Verilog
☆3,675Oct 12, 2026Updated this week
Alternatives and similar repositories for iverilog
Users that are interested in iverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilator open-source SystemVerilog simulator and lint system☆4,008Updated this week
- Yosys Open SYnthesis Suite☆4,803Updated this week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,031Updated this week
- cocotb: Python-based chip (RTL) verification☆2,539Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,958Sep 23, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VHDL 2008/93/87 simulator☆2,905Updated this week
- SystemVerilog compiler and language services☆1,161Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,391Sep 7, 2026Updated last month
- Chisel: A Modern Hardware Design Language☆4,808Updated this week
- nextpnr portable FPGA place and route tool☆1,771Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,273Updated this week
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Mar 2, 2023Updated 3 years ago
- SystemVerilog to Verilog conversion☆755Aug 18, 2026Updated last month
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,475Sep 25, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,884Sep 13, 2026Updated last month
- The MyHDL development repository☆1,131Sep 14, 2026Updated 3 weeks ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,758Updated this week
- Scala based HDL☆2,053Oct 6, 2026Updated last week
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,283Sep 27, 2026Updated 2 weeks ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,189Oct 5, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,238Updated this week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆632Mar 15, 2018Updated 8 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆556Sep 19, 2026Updated 3 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,156Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,966Mar 25, 2026Updated 6 months ago
- A small, light weight, RISC CPU soft core☆1,590Sep 16, 2026Updated 3 weeks ago
- Verilog Ethernet components for FPGA implementation☆3,123Feb 27, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆399Updated this week
- Verilog library for ASIC and FPGA designers☆1,442May 8, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,623Updated this week
- Digital timing diagram rendering engine☆3,507Aug 31, 2026Updated last month
- A Python toolbox for building complex digital hardware☆1,330Jan 5, 2026Updated 9 months ago
- Hardware Description Languages☆1,181Jul 9, 2026Updated 3 months ago
- Build your hardware, easily!☆4,155Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,721Sep 24, 2026Updated 2 weeks ago
- SystemVerilog language server☆586Sep 14, 2026Updated 3 weeks ago