fusesoc / fusesoc-coresLinks
FuseSoC standard core library
☆151Updated last month
Alternatives and similar repositories for fusesoc-cores
Users that are interested in fusesoc-cores are comparing it to the libraries listed below
Sorting:
- Verilog wishbone components☆123Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- ☆88Updated 3 months ago
- SoC based on VexRiscv and ICE40 UP5K☆161Updated 9 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- ☆137Updated last year
- Yet Another RISC-V Implementation☆99Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Verilog digital signal processing components☆168Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆144Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆73Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Control and Status Register map generator for HDL projects☆128Updated 7 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Updated 5 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆106Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- A curated list of awesome resources for HDL design and verification☆166Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- FPGA tool performance profiling☆104Updated last year
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago