Alternatives and similar repositories for fusesoc-cores

Users that are interested in fusesoc-cores are comparing it to the libraries listed below

• pieter3d / simview
  ☆79Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆121Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 3 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆139Updated 2 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆181Updated 6 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆151Updated last week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆190Updated this week
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆153Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 9 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆213Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated 9 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆71Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆113Updated 3 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆94Updated 9 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆79Updated 3 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago