Alternatives and similar repositories for fusesoc-cores

Users that are interested in fusesoc-cores are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆116Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆140Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 4 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆106Updated 4 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆182Updated 7 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• pieter3d / simview
  ☆79Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆156Updated last week
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆122Updated 2 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆146Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 2 weeks ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆152Updated 3 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated 10 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆72Updated last week
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆107Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆224Updated last week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆191Updated this week
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆121Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆179Updated 2 months ago