fusesoc / fusesoc-coresLinks
FuseSoC standard core library
☆143Updated 3 weeks ago
Alternatives and similar repositories for fusesoc-cores
Users that are interested in fusesoc-cores are comparing it to the libraries listed below
Sorting:
- Verilog wishbone components☆115Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- Control and Status Register map generator for HDL projects☆116Updated 3 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆121Updated last month
- Control and status register code generator toolchain☆138Updated 3 weeks ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 6 months ago
- ☆79Updated last year
- SystemVerilog synthesis tool☆196Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆240Updated 8 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆219Updated last week
- Example LED blinking project for your FPGA dev board of choice☆177Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆122Updated 3 weeks ago
- An Open Source configuration of the Arty platform☆129Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- Generic Register Interface (contains various adapters)☆121Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- FPGA tool performance profiling☆102Updated last year
- ☆133Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Announcements related to Verilator☆39Updated 5 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆177Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated this week
- SystemVerilog frontend for Yosys☆123Updated this week
- OSVVM Documentation☆34Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆67Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Yet Another RISC-V Implementation☆93Updated 9 months ago