fusesoc / fusesoc-cores
FuseSoC standard core library
☆115Updated last month
Related projects ⓘ
Alternatives and complementary repositories for fusesoc-cores
- ☆76Updated 8 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆71Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆110Updated 4 months ago
- FPGA tool performance profiling☆102Updated 9 months ago
- A utility for Composing FPGA designs from Peripherals☆169Updated 10 months ago
- Verilog wishbone components☆109Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- Mutation Cover with Yosys (MCY)☆77Updated 2 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆67Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆134Updated last year
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- Fabric generator and CAD tools☆148Updated 2 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- An Open Source configuration of the Arty platform☆122Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆53Updated 4 months ago
- Yet Another RISC-V Implementation☆85Updated 2 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆62Updated last year
- ☆63Updated 4 months ago
- Control and status register code generator toolchain☆105Updated 2 months ago
- TCP/IP controlled VPI JTAG Interface.☆60Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆150Updated 7 months ago
- A curated list of awesome resources for HDL design and verification☆140Updated this week
- Mathematical Functions in Verilog☆86Updated 3 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆76Updated 4 years ago