csail-csg / riscy-OOOLinks
RiscyOO: RISC-V Out-of-Order Processor
☆164Updated 5 years ago
Alternatives and similar repositories for riscy-OOO
Users that are interested in riscy-OOO are comparing it to the libraries listed below
Sorting:
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- RISC-V Torture Test☆202Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆161Updated 3 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆273Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆245Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- ☆189Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- RISC-V Formal Verification Framework☆164Updated last week
- ☆89Updated 2 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆104Updated 2 weeks ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- A teaching-focused RISC-V CPU design used at UC Davis☆151Updated 2 years ago
- Main page☆128Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- ☆87Updated 2 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Instruction Set Generator initially contributed by Futurewei☆298Updated 2 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆142Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- A Tiny Processor Core☆114Updated 3 months ago
- ☆247Updated 2 years ago
- RISC-V Virtual Prototype☆179Updated 10 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆215Updated last year