RiscyOO: RISC-V Out-of-Order Processor
☆172Jul 3, 2020Updated 6 years ago
Alternatives and similar repositories for riscy-OOO
Users that are interested in riscy-OOO are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆93Jul 29, 2019Updated 7 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆192Apr 4, 2026Updated 6 months ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆18Feb 20, 2020Updated 6 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆25Aug 24, 2024Updated 2 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,215Oct 3, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Riscy Processors - Open-Sourced RISC-V Processors☆74Apr 4, 2019Updated 7 years ago
- Bluespec BSV HLHDL tutorial☆117Mar 29, 2016Updated 10 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,261Oct 8, 2026Updated last week
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆343Jan 23, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆384Oct 19, 2023Updated 2 years ago
- VeeR EL2 Core☆347Updated this week
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆20Jul 4, 2025Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,314Updated this week
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,162Updated this week
- ☆111Oct 19, 2018Updated 7 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆257Sep 24, 2026Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,007Nov 15, 2024Updated last year
- RISC5Verilog for Pipistrello using lpddr memory☆14May 27, 2020Updated 6 years ago
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆11Jul 23, 2016Updated 10 years ago
- VeeR EH1 core☆971Jul 16, 2026Updated 3 months ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆53Aug 24, 2024Updated 2 years ago
- MR1 formally verified RISC-V CPU☆60Dec 16, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A teaching-focused RISC-V CPU design used at UC Davis☆157Feb 5, 2023Updated 3 years ago
- The OpenPiton Platform☆833Feb 25, 2026Updated 7 months ago
- ☆35Nov 4, 2024Updated last year
- A core language for rule-based hardware design 🦑☆189Dec 10, 2025Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated 3 weeks ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆17Aug 24, 2024Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆645Sep 14, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆109Jul 3, 2026Updated 3 months ago
- ☆17Jan 12, 2021Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,315Sep 18, 2021Updated 5 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆20Jul 17, 2019Updated 7 years ago
- Bluespec Compiler (BSC)☆1,145Oct 3, 2026Updated 2 weeks ago
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated last year
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago