csail-csg / riscy-OOOLinks
RiscyOO: RISC-V Out-of-Order Processor
☆164Updated 5 years ago
Alternatives and similar repositories for riscy-OOO
Users that are interested in riscy-OOO are comparing it to the libraries listed below
Sorting:
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- RISC-V Torture Test☆200Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated 3 weeks ago
- ☆89Updated last month
- ☆190Updated last year
- RISC-V Formal Verification Framework☆156Updated last week
- A teaching-focused RISC-V CPU design used at UC Davis☆151Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 11 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- ☆86Updated 4 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆214Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Instruction Set Generator initially contributed by Futurewei☆295Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Main page☆128Updated 5 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆86Updated last week
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- RISC-V Packed SIMD Extension☆152Updated last year
- ☆147Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 2 weeks ago
- A RISC-V Core (RV32I) written in Chisel HDL☆105Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago
- RISC-V Virtual Prototype☆179Updated 10 months ago