Alternatives and similar repositories for mor1kx

Users that are interested in mor1kx are comparing it to the libraries listed below

• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆668Updated 2 weeks ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated last year
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆870Updated 5 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆603Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆348Updated 2 weeks ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆716Updated 4 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆409Updated 6 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆716Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,086Updated last month
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆326Updated 3 years ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆924Updated 7 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆711Updated 2 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆373Updated last year
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,423Updated 5 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated 10 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 2 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,307Updated 3 weeks ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆171Updated 9 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆429Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆239Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆503Updated 7 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,309Updated last year
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 8 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆581Updated 4 years ago