openrisc / mor1kx
mor1kx - an OpenRISC 1000 processor IP core
☆528Updated 3 weeks ago
Alternatives and similar repositories for mor1kx:
Users that are interested in mor1kx are comparing it to the libraries listed below
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆649Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,045Updated 2 months ago
- RISC-V Formal Verification Framework☆596Updated 3 years ago
- The root repo for lowRISC project and FPGA demos.☆596Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆906Updated 5 months ago
- OpenRISC 1200 implementation☆164Updated 9 years ago
- VeeR EH1 core☆867Updated last year
- RISC-V CPU Core☆321Updated 10 months ago
- educational microarchitectures for risc-v isa☆711Updated last month
- Common SystemVerilog components☆601Updated this week
- The OpenPiton Platform☆695Updated last month
- Support for Rocket Chip on Zynq FPGAs☆407Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,092Updated 2 months ago
- A directory of Western Digital’s RISC-V SweRV Cores☆863Updated 5 years ago
- Bus bridges and other odds and ends☆542Updated this week
- 32-bit Superscalar RISC-V CPU☆994Updated 3 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆678Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆418Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆567Updated this week
- SystemVerilog to Verilog conversion☆615Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆521Updated this week
- RISC-V Cores, SoC platforms and SoCs☆870Updated 4 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆490Updated 4 months ago
- Verilog library for ASIC and FPGA designers☆1,271Updated 11 months ago
- A simple RISC-V processor for use in FPGA designs.☆270Updated 8 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,252Updated last week
- Linux on LiteX-VexRiscv☆627Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,512Updated 2 weeks ago