openrisc / mor1kx

Related projects ⓘ

Alternatives and complementary repositories for mor1kx

• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆959Updated 3 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆584Updated 2 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆818Updated last year
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆597Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆687Updated 2 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆855Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆287Updated 5 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆642Updated 3 weeks ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆159Updated 8 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆860Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆485Updated 9 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆386Updated 2 weeks ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆394Updated 5 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆513Updated this week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆729Updated 2 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,199Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆356Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,095Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆620Updated this week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆309Updated 2 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆451Updated 6 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆403Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,183Updated 6 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆774Updated last week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆263Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆520Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆545Updated 3 months ago