mor1kx - an OpenRISC 1000 processor IP core
☆577Aug 21, 2025Updated 6 months ago
Alternatives and similar repositories for mor1kx
Users that are interested in mor1kx are comparing it to the libraries listed below
Sorting:
- OpenRISC 1200 implementation☆178Nov 11, 2015Updated 10 years ago
- Core description files for FuseSoC☆125Jun 26, 2020Updated 5 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 2 months ago
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year
- OpenRISC processor IP core based on Tomasulo algorithm☆35Feb 18, 2022Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆684Jul 16, 2025Updated 7 months ago
- VeeR EL2 Core☆318Feb 23, 2026Updated last week
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆417Feb 20, 2026Updated last week
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- OpenRISC Tutorials☆48Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,389Feb 13, 2026Updated 2 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated last week
- The OpenPiton Platform☆772Feb 25, 2026Updated last week
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- An open source GPU based off of the AMD Southern Islands ISA.☆1,336Aug 18, 2025Updated 6 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,493Jan 7, 2026Updated last month
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- GPGPU microprocessor architecture☆2,179Nov 8, 2024Updated last year
- The original high performance and small footprint system-on-chip based on Migen™☆343Jan 5, 2026Updated 2 months ago
- Rocket Chip Generator☆3,696Feb 25, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated 2 weeks ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,208Feb 26, 2026Updated last week
- The OpenRISC 1000 architectural simulator☆77Apr 27, 2025Updated 10 months ago
- Yosys Open SYnthesis Suite☆4,305Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 3 weeks ago
- GPL v3 2D/3D graphics engine in verilog☆689Aug 31, 2014Updated 11 years ago
- LatticeMico32 soft processor☆106Oct 10, 2014Updated 11 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,152Feb 21, 2026Updated last week