An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
☆52Aug 24, 2024Updated 2 years ago
Alternatives and similar repositories for T13x
Users that are interested in T13x are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆19Jul 4, 2025Updated last year
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated 2 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆24Aug 24, 2024Updated 2 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- RISCV implementation in Verilog (RV32I spec)☆17Nov 5, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Flat Shade Society - Solskogen 2019 invite☆10Oct 2, 2019Updated 6 years ago
- "Okiedokie" by Soopadoopa☆14Aug 22, 2020Updated 6 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆81Oct 1, 2022Updated 3 years ago
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆11Jul 23, 2016Updated 10 years ago
- The winning Assembly Summer 2015 4k intro by Prismbeings.☆22Jun 29, 2016Updated 10 years ago
- Amoeba by Excess☆18Jun 7, 2022Updated 4 years ago
- ☆11Nov 19, 2019Updated 6 years ago
- ☆11Nov 19, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 1k by ferris and decypher☆11Jul 22, 2020Updated 6 years ago
- A sample implementation for todo-app using next.js, redux and typescript.☆20Jun 27, 2021Updated 5 years ago
- 🇲🇺 A list of cool open-source projects made in Mauritius☆13Oct 26, 2023Updated 2 years ago
- VeeR EH2 core☆276Jul 20, 2026Updated last month
- Ninjadev's new school demo "Construct" for Solskogen 2019☆13Jul 14, 2019Updated 7 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 8 years ago
- Distributed Systems Project for the 2019-2020 course of the Computer Science degree at the University of Havana, Cuba.☆12Feb 21, 2026Updated 6 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Progression of fuel prices in Mauritius (2002 - Present)☆12Aug 7, 2026Updated 3 weeks ago
- ☆15Jan 4, 2019Updated 7 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38May 28, 2026Updated 3 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆101Apr 25, 2026Updated 4 months ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- ☆147Apr 5, 2022Updated 4 years ago
- Solutions to activities for SOC 596: Computational Social Science.☆15Dec 2, 2016Updated 9 years ago
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆17Feb 22, 2019Updated 7 years ago
- RISC-V vector and other assembly code examples☆28Nov 4, 2020Updated 5 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Challenge source and solutions for InCTF junior (exclusively for Indian school students)☆33Sep 27, 2019Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆92Jul 29, 2019Updated 7 years ago
- e300 and u500 devkits☆10Nov 15, 2020Updated 5 years ago
- ☆30Jul 26, 2020Updated 6 years ago