klessydra / T13xLinks
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
☆45Updated last year
Alternatives and similar repositories for T13x
Users that are interested in T13x are comparing it to the libraries listed below
Sorting:
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 6 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 5 months ago
- A SystemVerilog source file pickler.☆60Updated last year
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆96Updated 8 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆104Updated 3 weeks ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆119Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- FPGA tool performance profiling☆103Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Simple runtime for Pulp platforms☆49Updated 2 weeks ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated 2 months ago
- Generic Register Interface (contains various adapters)☆133Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago