maltanar / axi-in-chisel
Examples for creating AXI-interfaced peripherals in Chisel
☆74Updated 9 years ago
Alternatives and similar repositories for axi-in-chisel:
Users that are interested in axi-in-chisel are comparing it to the libraries listed below
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Chisel components for FPGA projects☆122Updated last year
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- Python wrapper for verilator model☆82Updated last year
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆52Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Chisel Learning Journey☆108Updated 2 years ago
- Advanced Architecture Labs with CVA6☆57Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 3 months ago
- ☆43Updated 6 years ago
- ☆86Updated last year
- Altera Advanced Synthesis Cookbook 11.0☆102Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆189Updated this week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆70Updated this week
- Public release☆50Updated 5 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated last month
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆63Updated 7 months ago
- Xilinx AXI VIP example of use☆37Updated 3 years ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- ☆73Updated 10 years ago