maltanar / axi-in-chiselLinks
Examples for creating AXI-interfaced peripherals in Chisel
☆76Updated 9 years ago
Alternatives and similar repositories for axi-in-chisel
Users that are interested in axi-in-chisel are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Chisel components for FPGA projects☆126Updated last year
- A dynamic verification library for Chisel.☆155Updated 10 months ago
- Chisel Learning Journey☆110Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Public release☆57Updated 6 years ago
- Python wrapper for verilator model☆88Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Modular Multi-ported SRAM-based Memory☆31Updated 10 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated 3 weeks ago
- Bluespec BSV HLHDL tutorial☆108Updated 9 years ago
- ☆81Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆78Updated 10 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆16Updated 7 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- ☆97Updated last year
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆37Updated last year
- Various caches written in Verilog-HDL☆126Updated 10 years ago
- A Fast, Low-Overhead On-chip Network☆224Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week