Examples for creating AXI-interfaced peripherals in Chisel
☆75Nov 15, 2015Updated 10 years ago
Alternatives and similar repositories for axi-in-chisel
Users that are interested in axi-in-chisel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 2 years ago
- Chisel examples and code snippets☆277Aug 1, 2022Updated 3 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆178Jun 18, 2020Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆72Nov 7, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- ☆13May 8, 2025Updated 11 months ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆247Apr 29, 2024Updated 2 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- (System)Verilog to Chisel translator☆120May 20, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 10 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆31Sep 17, 2025Updated 7 months ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- Verilator Porcelain☆49Nov 7, 2023Updated 2 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repo has been put together to demonstrate a number of simple MIPS Processors written in Chisel.☆18Jul 9, 2021Updated 4 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆68Apr 29, 2026Updated last week
- Digital Design with Chisel☆914Updated this week
- educational microarchitectures for risc-v isa☆747Sep 1, 2025Updated 8 months ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- A multicore microprocessor test harness for measuring interference☆14Apr 16, 2020Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆91Apr 9, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- RISCV CPU implementation in SystemVerilog☆32Mar 17, 2026Updated last month
- A dynamic verification library for Chisel.☆162Nov 9, 2024Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆130Mar 6, 2026Updated 2 months ago
- CPU敏捷开发框架(龙芯杯2024)☆28Sep 6, 2024Updated last year