maltanar / fpga-tidbitsLinks
Chisel components for FPGA projects
☆128Updated 2 years ago
Alternatives and similar repositories for fpga-tidbits
Users that are interested in fpga-tidbits are comparing it to the libraries listed below
Sorting:
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆174Updated 5 years ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- Chisel Learning Journey☆111Updated 2 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- Public release☆58Updated 6 years ago
- Python wrapper for verilator model☆92Updated last year
- A Library of Chisel3 Tools for Digital Signal Processing☆242Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆160Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- An open-source UCIe controller implementation☆79Updated last week
- ☆20Updated 5 years ago
- ☆66Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago