Alternatives and similar repositories for pygears

Users that are interested in pygears are comparing it to the libraries listed below

• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆215Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆290Updated 3 months ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆90Updated 6 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆122Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 7 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆224Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 2 weeks ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 11 months ago
• phanrahan / magma
  magma circuits
  ☆261Updated 10 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated this week
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆46Updated 4 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆259Updated last month
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆303Updated 2 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated 2 months ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆88Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• idea-fasoc / fasoc
  ☆55Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 6 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year