bogdanvuk / pygearsLinks
HW Design: A Functional Approach
☆146Updated 2 years ago
Alternatives and similar repositories for pygears
Users that are interested in pygears are comparing it to the libraries listed below
Sorting:
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆219Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- Tools for working with circuits as graphs in python☆126Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆131Updated 3 weeks ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- Python wrapper for verilator model☆92Updated last year
- hardware library for hwt (= ipcore repo)☆43Updated last month
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 10 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆93Updated 6 years ago
- ideas and eda software for vlsi design☆50Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last week
- A complete open-source design-for-testing (DFT) Solution☆171Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- magma circuits☆263Updated last year
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆438Updated 3 months ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated 10 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- UVM 1.2 port to Python☆255Updated 10 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆127Updated 6 months ago
- This is a tutorial on standard digital design flow☆80Updated 4 years ago
- FuseSoC standard core library☆150Updated last week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- Next generation CGRA generator☆118Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆203Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month