Alternatives and similar repositories for pygears

Users that are interested in pygears are comparing it to the libraries listed below

• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆146Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆179Updated 5 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆271Updated 3 weeks ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆96Updated 6 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆138Updated last week
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆310Updated last week
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆51Updated 5 years ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated last week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆72Updated 8 months ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆123Updated 2 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆148Updated 11 months ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆244Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 4 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆280Updated 2 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 3 months ago
• intel / aib-phy-hardware
  ☆68Updated 3 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• themperek / cocotb-test
  Unit testing for cocotb
  ☆166Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Updated 8 months ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆93Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 3 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year