HW Design: A Functional Approach
☆146Jun 26, 2023Updated 3 years ago
Alternatives and similar repositories for pygears
Users that are interested in pygears are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 7 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Sep 20, 2026Updated 3 weeks ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆18Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- hardware library for hwt (= ipcore repo)☆45Sep 20, 2026Updated 3 weeks ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆29Oct 4, 2026Updated last week
- magma circuits☆264Oct 19, 2024Updated last year
- wavedrom to verilog converter☆18Sep 14, 2021Updated 5 years ago
- FPU Generator☆21Oct 4, 2026Updated last week
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆304Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆468Sep 10, 2026Updated last month
- Next generation CGRA generator☆119Updated this week
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆242Updated this week
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated 3 weeks ago
- System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…☆12Jun 2, 2016Updated 10 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- D3.js and ELK based schematic visualizer☆123May 13, 2026Updated 5 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Cross EDA Abstraction and Automation☆43Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- cocotb: Python-based chip (RTL) verification☆2,540Updated this week
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- Python interface to PCIE☆41Apr 30, 2018Updated 8 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆32Jul 12, 2024Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- ☆25Apr 18, 2021Updated 5 years ago
- 🔁 elastic circuit toolchain☆33Jul 20, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆631Jan 3, 2026Updated 9 months ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- みんなのSystemVerilog☆19May 12, 2022Updated 4 years ago
- Simple parser for extracting VHDL documentation☆75Jul 12, 2024Updated 2 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆328Aug 7, 2026Updated 2 months ago