Alternatives and similar repositories for pygears

Users that are interested in pygears are comparing it to the libraries listed below

• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆130Updated this week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆301Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆168Updated 2 months ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 9 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆264Updated this week
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆145Updated 9 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆237Updated 2 weeks ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆92Updated 6 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆46Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆254Updated 9 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆274Updated 2 weeks ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last month
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆142Updated last year
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆49Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆436Updated 2 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆181Updated 11 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆70Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆237Updated 2 months ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆163Updated 2 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆342Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 6 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆179Updated 11 months ago