Alternatives and similar repositories for vortexGPU

Users that are interested in vortexGPU are comparing it to the libraries listed below

• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆52Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆39Updated 7 years ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆34Updated last year
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆30Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆92Updated 5 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆39Updated 2 weeks ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• ryanmacdonald / Ray-Tracing-GPU
  RTL implementation of a ray-tracing GPU
  ☆13Updated 13 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆43Updated 11 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 11 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• embedded-explorer / Open-Source-RTL-Design
  This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
  ☆40Updated 4 years ago
• bradgrantham / alice5
  SPIR-V fragment shader GPU core based on RISC-V
  ☆43Updated 4 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆91Updated 5 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• SpinalHDL / SpinalDoc
  SpinalHDL documentation assets (pictures, slides, ...)
  ☆31Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆25Updated 3 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆67Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆73Updated 13 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago