Alternatives and similar repositories for d3-hwschematic

Users that are interested in d3-hwschematic are comparing it to the libraries listed below

• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 3 months ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆81Updated 2 years ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated last year
• pieter3d / simview
  ☆88Updated last month
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆65Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆162Updated last month
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆219Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆155Updated last week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 2 weeks ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆103Updated 9 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated 2 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆178Updated this week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 3 weeks ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆111Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆169Updated 3 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 3 weeks ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆122Updated last week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago