Nic30 / d3-hwschematic
D3.js and ELK based schematic visualizer
☆99Updated last year
Alternatives and similar repositories for d3-hwschematic:
Users that are interested in d3-hwschematic are comparing it to the libraries listed below
- D3.js based wave (signal) visualizer☆61Updated last year
- Web-based HDL diagramming tool☆79Updated last year
- ☆33Updated 5 months ago
- ☆31Updated last year
- ☆53Updated last year
- SystemVerilog frontend for Yosys☆80Updated this week
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆93Updated last month
- WAL enables programmable waveform analysis.☆147Updated 3 weeks ago
- Prefix tree adder space exploration library☆57Updated 4 months ago
- BAG framework☆40Updated 7 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆82Updated 10 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- A SystemVerilog source file pickler.☆55Updated 5 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆58Updated 2 weeks ago
- Fabric generator and CAD tools☆162Updated 3 weeks ago
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated 2 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆57Updated 4 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- SystemVerilog synthesis tool☆181Updated last week
- Announcements related to Verilator☆39Updated 4 years ago
- IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…☆32Updated 4 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆51Updated last year
- A Python package for testing hardware (part of the magma ecosystem)☆41Updated last year
- Control and status register code generator toolchain☆117Updated last week
- Introductory course into static timing analysis (STA).☆88Updated 4 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Python library for operations with VCD and other digital wave files☆47Updated 9 months ago
- A Standalone Structural Verilog Parser☆89Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆119Updated last week