Alternatives and similar repositories for d3-hwschematic

Users that are interested in d3-hwschematic are comparing it to the libraries listed below

• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆61Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆60Updated last week
• idea-fasoc / fasoc
  ☆54Updated last year
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated 6 months ago
• pulp-platform / cheshire-ihp130-o
  ☆38Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated last week
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆49Updated 11 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆78Updated 5 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆59Updated 3 weeks ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 10 months ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 5 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 3 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆51Updated 2 weeks ago
• fukatani / Pyverilog_toolbox
  ☆40Updated 6 years ago
• mineda-support / ICPS2023_5
  ☆52Updated 2 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆83Updated 9 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆149Updated 2 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 4 months ago