davidcastells / py4hwLinks
Hardware Design/Visualization/Simulation/RTLGeneration Framework
☆16Updated last week
Alternatives and similar repositories for py4hw
Users that are interested in py4hw are comparing it to the libraries listed below
Sorting:
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated this week
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated last week
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆24Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆88Updated 3 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- ☆33Updated last year
- A Risc-V SoC for Tiny Tapeout☆47Updated 2 months ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- Prefix tree adder space exploration library☆56Updated 2 weeks ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆64Updated 5 months ago
- ☆91Updated 3 months ago
- ☆38Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- An automatic clock gating utility☆52Updated 9 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V Nox core☆71Updated 6 months ago
- Fabric generator and CAD tools graphical frontend☆17Updated 6 months ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- hardware library for hwt (= ipcore repo)☆43Updated last month
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- SAR ADC on tiny tapeout☆45Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Updated 11 months ago