Alternatives and similar repositories for py4hw:

Users that are interested in py4hw are comparing it to the libraries listed below

• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆31Updated last week
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• tongchen126 / Boot-Debian-On-Litex-Rocket
  ☆13Updated 2 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated last week
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆24Updated 2 weeks ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆37Updated 3 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated this week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 7 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆51Updated last week
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 3 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆54Updated this week
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆40Updated 2 weeks ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆3Updated 3 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated 2 weeks ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• efabless / caravel_board
  ☆34Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆79Updated last week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year