davidcastells / py4hwLinks
Hardware Design/Visualization/Simulation/RTLGeneration Framework
☆16Updated last week
Alternatives and similar repositories for py4hw
Users that are interested in py4hw are comparing it to the libraries listed below
Sorting:
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- Characterizer☆28Updated 2 months ago
- Prefix tree adder space exploration library☆57Updated 8 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- ☆36Updated 8 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated this week
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆34Updated 3 weeks ago
- RISC-V Nox core☆66Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆72Updated 10 months ago
- hardware library for hwt (= ipcore repo)☆40Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆44Updated last month
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- ☆32Updated 6 months ago
- ☆47Updated 3 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Xilinx Unisim Library in Verilog☆79Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆95Updated last month
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated last week
- An automatic clock gating utility☆50Updated 3 months ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 5 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- An open-source HDL register code generator fast enough to run in real time.☆71Updated 3 weeks ago
- Cross EDA Abstraction and Automation☆39Updated last week
- ☆33Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago