Hardware Design/Visualization/Simulation/RTLGeneration Framework
☆16Feb 12, 2026Updated 2 weeks ago
Alternatives and similar repositories for py4hw
Users that are interested in py4hw are comparing it to the libraries listed below
Sorting:
- Reticle evaluation (PLDI 2021)☆12Apr 12, 2021Updated 4 years ago
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆26Mar 15, 2025Updated 11 months ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Feb 11, 2026Updated 2 weeks ago
- micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop☆18Feb 25, 2025Updated last year
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- Artix7 SOM☆18Sep 9, 2024Updated last year
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated last year
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- CRUVI Standard Specifications☆21May 6, 2024Updated last year
- Test of a RP2040 PMOD attached to a LiteX SoC.☆28May 16, 2023Updated 2 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- 2-layer and 4-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.☆20Jan 6, 2026Updated last month
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Feb 23, 2025Updated last year
- Toy nmigen RISC V rv32i implementation☆23Oct 24, 2023Updated 2 years ago
- ☆22Mar 5, 2022Updated 3 years ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆178Jan 16, 2026Updated last month
- Cross-platform Python client for the CodeReef.ai portal to manage portable workflows, reusable automation actions, software detection plu…☆11Mar 27, 2020Updated 5 years ago
- RISC-V soft core running on Colorlight 5B-74B.☆40Feb 14, 2021Updated 5 years ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 2 years ago
- A C++ to Verilog translation tool with some basic guarantees that your code will work.☆177Feb 23, 2025Updated last year
- MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems☆12Jun 20, 2024Updated last year
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- Open Source HVS for geiger counters.☆11Jan 20, 2026Updated last month
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- high abstraction synthesis☆14Apr 8, 2024Updated last year
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆13Feb 11, 2026Updated 2 weeks ago
- ☆12Mar 10, 2024Updated last year
- R for UX Research☆20Jan 27, 2025Updated last year
- ☆10Jul 30, 2020Updated 5 years ago
- assorted library of utility cores for amaranth HDL☆102Sep 17, 2024Updated last year
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆46Jan 16, 2023Updated 3 years ago
- I'm making a Github Pages repo!☆10Jun 8, 2016Updated 9 years ago
- mruby to C parser☆38Oct 19, 2014Updated 11 years ago
- "Talking PD" article code repository☆14Jun 23, 2023Updated 2 years ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆13Dec 15, 2025Updated 2 months ago
- ☆22Updated this week
- Neural machine translation with Recurrent Deterministic Policy Gradient☆10Aug 18, 2016Updated 9 years ago
- ☆14Nov 28, 2024Updated last year