Alternatives and similar repositories for sphinx-hwt

Users that are interested in sphinx-hwt are comparing it to the libraries listed below

• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated 2 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 5 months ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 5 years ago
• eine / hwd-ide
  ☆20Updated 5 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆64Updated 2 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 4 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆31Updated last month
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 3 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆59Updated last month
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆22Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆13Updated 2 weeks ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆82Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last month
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• wavedrom / datasheet
  datasheet generator
  ☆30Updated 5 months ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆38Updated 4 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• 0x01be / rudder
  Learn, share and collaborate on ASIC design using open tools and technologies
  ☆14Updated 5 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆32Updated 2 weeks ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 11 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• LaurentCabaret / pyVhdl2Sch
  pyVhdl2sch is a python based VHDL to (pdf) schematic converter
  ☆33Updated 6 years ago