Nic30 / hwtLib
hardware library for hwt (= ipcore repo)
☆34Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for hwtLib
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆63Updated 2 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆52Updated 3 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆31Updated last month
- Public repository for PySysC, (From SC Common Practices Subgroup)☆48Updated 10 months ago
- SystemVerilog Linter based on pyslang☆22Updated 7 months ago
- ☆30Updated last year
- ☆26Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆21Updated last month
- An open source, parameterized SystemVerilog digital hardware IP library☆22Updated 5 months ago
- YosysHQ SVA AXI Properties☆31Updated last year
- Import and export IP-XACT XML register models☆33Updated 3 weeks ago
- Python Tool for UVM Testbench Generation☆49Updated 5 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated 11 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆47Updated 4 months ago
- Open source process design kit for 28nm open process☆42Updated 6 months ago
- Running Python code in SystemVerilog☆62Updated 3 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 2 weeks ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆18Updated 9 years ago
- Python interface for cross-calling with HDL☆19Updated this week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆54Updated last year
- Open source RTL simulation acceleration on commodity hardware☆21Updated last year
- ☆39Updated 4 years ago
- Open FPGA Modules☆22Updated last month
- Announcements related to Verilator☆38Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆78Updated last month
- Platform Level Interrupt Controller☆35Updated 6 months ago
- An open-source HDL register code generator fast enough to run in real time.☆31Updated last week