azonenberg / antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
☆62Updated this week
Alternatives and similar repositories for antikernel-ipcores:
Users that are interested in antikernel-ipcores are comparing it to the libraries listed below
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 11 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Extensible FPGA control platform☆59Updated last year
- Wishbone interconnect utilities☆39Updated 2 months ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- A padring generator for ASICs☆25Updated last year
- Small footprint and configurable JESD204B core☆42Updated 3 months ago
- Project X-Ray Database: XC7 Series☆66Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆95Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Wishbone controlled I2C controllers☆47Updated 5 months ago
- USB Full Speed PHY☆42Updated 4 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- ☆39Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- ☆41Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- PicoRV☆44Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 3 weeks ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- A wishbone controlled scope for FPGA's☆78Updated last year
- Small footprint and configurable SPI core☆41Updated 3 months ago
- Virtual development board for HDL design☆41Updated 2 years ago
- Naive Educational RISC V processor☆79Updated 6 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- FPGA board-level debugging and reverse-engineering tool☆36Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year