Alternatives and similar repositories for sydpy

Users that are interested in sydpy are comparing it to the libraries listed below

• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆13Updated last month
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 3 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 11 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆31Updated 2 months ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆23Updated 2 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated last week
• idea-fasoc / fasoc
  ☆55Updated last year
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 2 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated this week
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆72Updated 10 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• dan-fritchman / Layout21
  Integrated Circuit Layout
  ☆54Updated 4 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆81Updated 3 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆18Updated 3 months ago
• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆29Updated this week
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated this week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago