bogdanvuk / sydpyLinks
System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to SystemVerilog and other HDLs.
☆12Updated 9 years ago
Alternatives and similar repositories for sydpy
Users that are interested in sydpy are comparing it to the libraries listed below
Sorting:
- Verification Utilities for MyHDL☆17Updated 2 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Updated 7 months ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- Contains examples to start with Kactus2.☆23Updated last year
- hardware library for hwt (= ipcore repo)☆43Updated last month
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated last month
- mantle library☆44Updated 3 years ago
- Example of how to use UVM with Verilator☆34Updated 2 months ago
- Cross EDA Abstraction and Automation☆41Updated 2 months ago
- IP-XACT XML binding library☆16Updated 9 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Digital Circuit rendering engine☆39Updated 6 months ago
- BAG framework☆41Updated last year
- ☆56Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Updated 4 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated 3 weeks ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Updated 2 years ago
- Interchange formats for chip design.☆36Updated last week
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Updated 10 months ago
- A Vivado HLS Command Line Helper Tool☆36Updated 4 years ago
- Debuggable hardware generator☆71Updated 2 years ago
- ☆31Updated 2 years ago
- Prefix tree adder space exploration library☆56Updated 2 weeks ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Updated 3 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year