System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to SystemVerilog and other HDLs.
☆12Jun 2, 2016Updated 10 years ago
Alternatives and similar repositories for sydpy
Users that are interested in sydpy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- use pivpi to drive testbench event☆21Jul 21, 2016Updated 10 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- DPI module for Ethernet-based interaction with Verilator simulations☆11Nov 1, 2012Updated 14 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆10May 27, 2026Updated 5 months ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- SystemVerilog stuff and stuff.☆12Jun 2, 2016Updated 10 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- A Python-based Spice Simulator☆11Jun 17, 2021Updated 5 years ago
- Implementing the Double-Slit experiment in Python☆12Jan 7, 2021Updated 5 years ago
- Coderefinery project website.☆11Oct 26, 2026Updated last week
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated 2 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 14 years ago
- A webBook authoring framework using jupyter notebooks☆13Jan 13, 2018Updated 8 years ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 3 years ago
- An example application using mongodb rust tide and handlebars A.K.A MoRTH stack☆14Nov 19, 2020Updated 5 years ago
- Python-based hardware modeling framework☆247Oct 27, 2019Updated 7 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆54Nov 21, 2016Updated 9 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- I2C eeprom device drivers (pure Python)☆12May 8, 2020Updated 6 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- Rust support for the open-source NEORV32 RISC-V microcontroller.☆14Feb 19, 2026Updated 8 months ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 12 years ago
- A pipelined MIPS processor implemented in Python☆25Mar 31, 2016Updated 10 years ago
- zig lang working with c lang☆13Aug 27, 2022Updated 4 years ago
- A pure python implementation of the Snappy compression algorithm.☆18Sep 29, 2021Updated 5 years ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 5 months ago
- Yet another IPython notebook to LaTeX converter - this one exports clean code easily absorbed in other reports.☆16Jun 1, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 7 years ago
- Provides a VXI-11 driver for controlling instruments over Ethernet☆14May 11, 2017Updated 9 years ago
- Low Precision Arithmetic Simulation in PyTorch - extension for posit and beyond☆16Dec 9, 2025Updated 10 months ago
- Complete simulation of IEEE 754 fixed and floating point specification to any precision☆13Aug 26, 2020Updated 6 years ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Snap! extension for LEGO BOOST☆13Oct 15, 2017Updated 9 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 16 years ago