wavedrom / verilogLinks
wavedrom to verilog converter
☆16Updated 3 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below
Sorting:
- Digital Circuit rendering engine☆39Updated last year
- Freecores website☆19Updated 8 years ago
- ☆17Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- GUI editor for hardware description designs☆28Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Simulation VCD waveform viewer, using old Motif UI☆26Updated 2 years ago
- ☆17Updated 2 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆29Updated last year
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Extended and external tests for Verilator testing☆16Updated 3 weeks ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Updated last year
- USB Full Speed PHY☆44Updated 5 years ago
- An open-source VHDL library for FPGA design.☆31Updated 3 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Tool to fetch and parse data about Efabless MPW projects☆15Updated 2 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- understanding the tinyfpga bootloader☆24Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- datasheet generator☆28Updated 2 weeks ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- ☆12Updated 4 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 5 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆54Updated 2 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆21Updated 10 months ago