wavedrom / verilogLinks
wavedrom to verilog converter
☆17Updated 4 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below
Sorting:
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- Digital Circuit rendering engine☆39Updated 6 months ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 weeks ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- Template project for LiteX-based SoCs☆20Updated 3 weeks ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago
- GUI editor for hardware description designs☆30Updated 2 years ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆35Updated last year
- ☆18Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆54Updated 3 weeks ago
- An open-source VHDL library for FPGA design.☆32Updated 3 years ago
- sample VCD files☆40Updated last month
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 weeks ago
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- Bit streams forthe Ulx3s ECP5 device☆18Updated 2 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- ☆18Updated 5 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- ☆20Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 months ago
- FPGA board-level debugging and reverse-engineering tool☆39Updated 2 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 5 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 4 years ago