Alternatives and similar repositories for verilog:

Users that are interested in verilog are comparing it to the libraries listed below

• drom / logidrom
  Digital Circuit rendering engine
  ☆36Updated last year
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 weeks ago
• albaEDA / Nirah
  Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…
  ☆12Updated 5 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last week
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 4 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆27Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• mithro / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆17Updated 5 years ago
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆25Updated last year
• 0x01be / rudder
  Learn, share and collaborate on ASIC design using open tools and technologies
  ☆13Updated 4 years ago
• julianfl0w / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆13Updated 2 years ago
• wavedrom / datasheet
  datasheet generator
  ☆28Updated 6 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆42Updated 4 years ago
• EvgenyMuryshkin / qusoc
  QuSoC demo projects and template
  ☆21Updated 7 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆26Updated 10 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• Nic30 / sphinx-hwt
  Sphinx extension for visual documentation of hardware written in HWT
  ☆11Updated 7 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated 11 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆16Updated 4 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week