Alternatives and similar repositories for verilog

Users that are interested in verilog are comparing it to the libraries listed below

• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆26Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆59Updated last month
• gnuradio / gr-verilog
  ☆18Updated 2 years ago
• Digilent / Arty-A7-35-XADC
  ☆19Updated 4 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 months ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 6 years ago
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆32Updated 11 months ago
• wavedrom / datasheet
  datasheet generator
  ☆28Updated last week
• albaEDA / Nirah
  Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…
  ☆12Updated 6 years ago
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆28Updated last year
• controlpaths / litefury_rp5
  Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1
  ☆29Updated last year
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 7 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• psychogenic / microcotb
  micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
  ☆14Updated 4 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆21Updated 5 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆27Updated 5 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last month
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 4 years ago
• sergachev / litex-template
  Template project for LiteX-based SoCs
  ☆21Updated last week