Python interface to PCIE
☆40Apr 30, 2018Updated 7 years ago
Alternatives and similar repositories for python-pci
Users that are interested in python-pci are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- JESD204 Eye Scan Visualization Utility☆18Apr 6, 2026Updated 3 weeks ago
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆19Jul 10, 2020Updated 5 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 8 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 10 years ago
- ☆11Jan 8, 2021Updated 5 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Feb 20, 2026Updated 2 months ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- TMDS encoding tools☆17Jan 11, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Apr 7, 2020Updated 6 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Nov 25, 2015Updated 10 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 5 years ago
- MicroPython on FPGA☆13Jul 11, 2016Updated 9 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- BNG/PPPoE P4 software☆18Mar 20, 2020Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆37Dec 24, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- JESD204B core for Migen/MiSoC☆36May 5, 2021Updated 4 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆23Dec 14, 2018Updated 7 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 12 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 10 years ago
- ESP32 fork of Micro QuickJS Javascript Engine☆23Dec 29, 2025Updated 4 months ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆59Mar 16, 2023Updated 3 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year