davidthings / hdelk

Related projects: ⓘ

• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 3 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆61Updated 6 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆52Updated 11 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆40Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆68Updated 2 years ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 11 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆48Updated 2 weeks ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆75Updated 4 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆58Updated 7 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆77Updated 2 months ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆96Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆31Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆107Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆34Updated last year
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆22Updated 2 years ago
• bmpenuelas / waveform-render-vscode
  Render waveforms inside VSCode with WaveDrom
  ☆34Updated last month
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated 3 weeks ago
• Nic30 / d3-hwschematic
  D3.js and ELK based schematic visualizer
  ☆89Updated 6 months ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 7 years ago
• Gekkio / docker-fpga
  Dockerized FPGA toolchain experiments
  ☆27Updated 7 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆28Updated 2 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• BreizhGeek / wavedrompy
  ☆20Updated this week
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 11 months ago
• TerosTechnology / colibri
  ☆17Updated last year
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆40Updated 3 months ago
• olofk / observer
  ☆40Updated 4 years ago
• albaEDA / Nirah
  Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…
  ☆12Updated 5 years ago