Alternatives and similar repositories for hdelk

Users that are interested in hdelk are comparing it to the libraries listed below

• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 5 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆65Updated 2 years ago
• Nic30 / d3-hwschematic
  D3.js and ELK based schematic visualizer
  ☆112Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆49Updated 3 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 5 months ago
• wavedrom / cli
  CLI for WaveDrom
  ☆64Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆119Updated last year
• pieter3d / simview
  ☆88Updated 3 months ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 4 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 5 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated last month
• mattvenn / simulate-gate
  Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
  ☆14Updated 6 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆32Updated last month
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆112Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆89Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆81Updated last month
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆108Updated last week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 3 weeks ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 5 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆85Updated last year
• LaurentCabaret / pyVhdl2Sch
  pyVhdl2sch is a python based VHDL to (pdf) schematic converter
  ☆33Updated 6 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆56Updated this week
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated this week