davidthings / hdelk
Web-based HDL diagramming tool
☆79Updated last year
Alternatives and similar repositories for hdelk:
Users that are interested in hdelk are comparing it to the libraries listed below
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 4 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆59Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆43Updated 6 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆44Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆111Updated 5 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆58Updated last week
- Project X-Ray Database: XC7 Series☆66Updated 3 years ago
- CLI for WaveDrom☆61Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- WAL enables programmable waveform analysis.☆147Updated 3 weeks ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- ☆77Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆45Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated last week
- Mutation Cover with Yosys (MCY)☆80Updated last week
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- D3.js based wave (signal) visualizer☆61Updated last year
- FPGA and Digital ASIC Build System☆74Updated this week
- A JSON library implemented in VHDL.☆78Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆39Updated last year
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆75Updated 3 years ago
- Ultimate ECP5 development board☆104Updated 5 years ago
- An abstract language model of VHDL written in Python.☆51Updated this week
- System on Chip toolkit for Amaranth HDL☆86Updated 5 months ago