Web-based HDL diagramming tool
β85May 1, 2023Updated 3 years ago
Alternatives and similar repositories for hdelk
Users that are interested in hdelk are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- D3.js and ELK based schematic visualizerβ122May 13, 2026Updated 2 months ago
- π Zoomable Waveform viewer for the Webβ43Nov 3, 2020Updated 5 years ago
- Python script to transform a VCD file to wavedrom formatβ85Aug 18, 2022Updated 3 years ago
- Cross EDA Abstraction and Automationβ42Nov 17, 2025Updated 8 months ago
- πΎ Design βͺ Hardwareβ79Jul 1, 2026Updated 2 weeks ago
- Managed Kubernetes at scale on DigitalOcean β’ AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workβ¦β10Jan 13, 2022Updated 4 years ago
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- HTML & Js based VCD viewerβ83Feb 16, 2026Updated 5 months ago
- sample VCD filesβ43Feb 13, 2026Updated 5 months ago
- Sticky sticky PCIβ10Oct 25, 2018Updated 7 years ago
- Determines the modules declared and instantiated in a SystemVerilog fileβ51Sep 23, 2024Updated last year
- D3.js based wave (signal) visualizerβ68Jun 9, 2026Updated last month
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4β330Jun 30, 2025Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.β38Apr 9, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer β’ AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL Code for infrastructural blocks (designed for FPGA)β15Oct 26, 2022Updated 3 years ago
- Yosys plugin for synthesis of Bluespec codeβ16Sep 8, 2021Updated 4 years ago
- wavedrom to verilog converterβ17Sep 14, 2021Updated 4 years ago
- Atom Hardware IDEβ13May 4, 2021Updated 5 years ago
- FuseSoc Verification Automationβ22Jul 21, 2022Updated 4 years ago
- Sphinx extension for visual documentation of hardware written in HWTβ12Nov 12, 2025Updated 8 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++β226Jun 22, 2026Updated 3 weeks ago
- Python library for operations with VCD and other digital wave filesβ55May 19, 2026Updated 2 months ago
- A library and command-line tool for querying a Verilog netlist.β30Jun 13, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways β’ AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Sphinx Extension which generates various types of diagrams from Verilog code.β65Sep 25, 2023Updated 2 years ago
- Digital Circuit rendering engineβ40Jul 9, 2026Updated last week
- Fixed point package for Python.β37Apr 28, 2023Updated 3 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.gitβ15May 21, 2018Updated 8 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposesβ69Updated this week
- Unit testing for cocotbβ173Apr 18, 2026Updated 3 months ago
- Trying to verify Verilog/VHDL designs with formal methods and toolsβ43Mar 7, 2024Updated 2 years ago
- Open Source Verification Bundle for VHDL and System Verilogβ48Jan 12, 2024Updated 2 years ago
- VHDLproc is a VHDL preprocessorβ24May 12, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI β’ AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A JSON library implemented in VHDL.β85Jul 13, 2026Updated last week
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation fasterβ11Oct 14, 2021Updated 4 years ago
- This is an OOT module for GNU Radio integrating verilog simulation featureβ38Sep 23, 2019Updated 6 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)β69Feb 16, 2026Updated 5 months ago
- Value Change Dump (VCD) parserβ38Jan 9, 2026Updated 6 months ago
- Industry standard I/O for nMigenβ12Apr 23, 2020Updated 6 years ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.β259Jun 30, 2026Updated 3 weeks ago