autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
☆15May 21, 2018Updated 7 years ago
Alternatives and similar repositories for coriolis
Users that are interested in coriolis are comparing it to the libraries listed below
Sorting:
- Free open source EDA tools☆66Oct 1, 2019Updated 6 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Magic VLSI Layout Tool☆21Oct 10, 2019Updated 6 years ago
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 6 years ago
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Apr 23, 2010Updated 15 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)☆15Jan 5, 2026Updated 2 months ago
- Libre Silicon Compiler☆22Apr 13, 2021Updated 4 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- ☆30Aug 19, 2019Updated 6 years ago
- ☆19Oct 28, 2024Updated last year
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- This library is a low level parser for the OpenAccess file format.☆16Jun 24, 2017Updated 8 years ago
- ☆91Aug 17, 2019Updated 6 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- ☆114Feb 2, 2021Updated 5 years ago
- 1st Testwafer for LibreSilicon☆28Aug 2, 2019Updated 6 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- Verilog Plugin for Intellij IDEA☆10Oct 22, 2020Updated 5 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62May 28, 2024Updated last year
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- ☆57Sep 30, 2023Updated 2 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Jun 25, 2020Updated 5 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 10 years ago
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- EDA Analytics Central☆17Dec 8, 2022Updated 3 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- Copyleftist's Standard Cell Library☆101May 2, 2024Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆34Dec 25, 2025Updated 2 months ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- A frontend for NgSpice. (Archived and no longer maintained)☆25Mar 12, 2019Updated 7 years ago