libresilicon / coriolis
autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
☆15Updated 6 years ago
Alternatives and similar repositories for coriolis:
Users that are interested in coriolis are comparing it to the libraries listed below
- Magic VLSI Layout Tool☆21Updated 5 years ago
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago
- IRSIM switch-level simulator for digital circuits☆31Updated 8 months ago
- Free open source EDA tools☆65Updated 5 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 5 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆12Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- ☆22Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 8 months ago
- Cross EDA Abstraction and Automation☆36Updated last month
- A framework for FPGA emulation of mixed-signal systems☆34Updated 3 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- ☆11Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 3 weeks ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last month
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Extended and external tests for Verilator testing☆16Updated last week
- SRAM build space for the GF180MCU provided by GlobalFoundries.☆10Updated 2 years ago
- ☆15Updated 2 months ago
- A Verilog Synthesis Regression Test☆35Updated 9 months ago
- Open Source Detailed Placement engine☆11Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 4 years ago