libresilicon / coriolisLinks
autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
☆15Updated 7 years ago
Alternatives and similar repositories for coriolis
Users that are interested in coriolis are comparing it to the libraries listed below
Sorting:
- Free open source EDA tools☆66Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆34Updated 4 months ago
- The source code that empowers OpenROAD Cloud☆12Updated 5 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- Magic VLSI Layout Tool☆21Updated 5 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆12Updated 9 years ago
- ☆18Updated 4 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 5 years ago
- ☆23Updated 3 months ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- ☆18Updated 10 months ago
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆11Updated 2 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆14Updated 2 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Libre Silicon Compiler☆22Updated 4 years ago
- A bit-serial CPU☆19Updated 5 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated last month
- Collection of test cases for Yosys☆18Updated 3 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year
- Icarus SIMBUS☆19Updated 5 years ago
- ☆18Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆57Updated 5 years ago