Alternatives and similar repositories for coriolis:

Users that are interested in coriolis are comparing it to the libraries listed below

• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 10 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last week
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆12Updated 5 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 10 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• verilog-to-routing / libsdcparse
  ☆11Updated 5 years ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 5 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• fusesoc / fusesoc-generators
  A collection of core generators to use with FuseSoC
  ☆15Updated 7 months ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• Xyce / Xyce_Regression
  The test suite for the Xyce Parallel Electronic Simulator
  ☆4Updated 2 weeks ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 5 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• steveicarus / simbus
  Icarus SIMBUS
  ☆18Updated 5 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆12Updated 5 years ago
• Qucs / qucs-help
  Qucs-Help documentation
  ☆11Updated 6 years ago
• efabless / caravel-lite
  ☆15Updated 4 months ago
• Qucs / gnucsator
  This package provides a gnucap based qucsator implementation.
  ☆13Updated last month
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated last year