libresilicon / coriolis
autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
☆15Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for coriolis
- Magic VLSI Layout Tool☆20Updated 5 years ago
- The source code that empowers OpenROAD Cloud☆11Updated 4 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 5 years ago
- Qucs-Help documentation☆11Updated 6 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Benchmarks for Yosys development☆22Updated 4 years ago
- Free open source EDA tools☆64Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆30Updated 6 months ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆12Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 7 years ago
- ☆11Updated 4 years ago
- System on Chip toolkit for nMigen☆20Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆14Updated 2 years ago
- ☆22Updated last year
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆17Updated 5 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆11Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Cross EDA Abstraction and Automation☆36Updated this week
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated last year
- Collection of test cases for Yosys☆17Updated 2 years ago
- A collection of core generators to use with FuseSoC☆13Updated 3 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- The test suite for the Xyce Parallel Electronic Simulator☆3Updated 3 weeks ago