Alternatives and similar repositories for hwtHls:

Users that are interested in hwtHls are comparing it to the libraries listed below

• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆30Updated 3 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated last month
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 4 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆18Updated last month
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• pulp-platform / svase
  ☆31Updated last month
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated last week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆36Updated 3 months ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 11 months ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 4 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 3 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago