LLVM based HLS library for HWToolkit (hardware devel. toolkit)
☆29May 13, 2026Updated last week
Alternatives and similar repositories for hwtHls
Users that are interested in hwtHls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 3 months ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 months ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- A collection of core generators to use with FuseSoC☆18Aug 23, 2024Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Mar 11, 2024Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Verilog generation tool written in Rust☆62Jun 29, 2023Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 6 months ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- hardware library for hwt (= ipcore repo)☆44May 13, 2026Updated last week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 4 years ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- OpenFPGA☆34Mar 12, 2018Updated 8 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- Verilog parsing and generator crate.☆22Apr 16, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V kernel step-by-step implmenetation☆12Nov 12, 2019Updated 6 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆325Jun 30, 2025Updated 10 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- 書籍「作ろう！CPU」のサンプルコード☆11Jan 23, 2021Updated 5 years ago
- autonomous driving contest reference kit☆10Dec 2, 2021Updated 4 years ago
- Add support for debugging JITed code to ORC JIT from LLVM Kaleidoscope example☆13Jun 14, 2017Updated 8 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆37Updated this week
- HW Design: A Functional Approach☆145Jun 26, 2023Updated 2 years ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- CMurphi mirror: http://mclab.di.uniroma1.it/site/index.php/software/18-cmurphi☆14Jan 22, 2016Updated 10 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆133May 19, 2022Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Dec 17, 2025Updated 5 months ago
- Docker image for writing environment for Japanese documents with LaTeX / TeX Live☆11Oct 29, 2023Updated 2 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated last year