Alternatives and similar repositories for hwtHls

Users that are interested in hwtHls are comparing it to the libraries listed below

• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• pulp-platform / svase
  ☆33Updated 11 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• fukatani / Pyverilog_toolbox
  ☆43Updated 7 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆28Updated 2 months ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆127Updated 2 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆27Updated 2 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆49Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆36Updated 2 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆32Updated 4 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆53Updated 2 years ago