LLVM based HLS library for HWToolkit (hardware devel. toolkit)
☆28Jan 21, 2026Updated 2 months ago
Alternatives and similar repositories for hwtHls
Users that are interested in hwtHls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- A collection of core generators to use with FuseSoC☆18Aug 23, 2024Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆223Dec 23, 2025Updated 3 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Mar 11, 2024Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Verilog generation tool written in Rust☆62Jun 29, 2023Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 4 months ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 5 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- OpenFPGA☆34Mar 12, 2018Updated 8 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Dec 5, 2023Updated 2 years ago
- Verilog parsing and generator crate.☆21Apr 16, 2020Updated 5 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- RISC-V kernel step-by-step implmenetation☆12Nov 12, 2019Updated 6 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆321Jun 30, 2025Updated 8 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- 書籍「作ろう！CPU」のサンプルコード☆11Jan 23, 2021Updated 5 years ago
- autonomous driving contest reference kit☆10Dec 2, 2021Updated 4 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Feb 11, 2026Updated last month
- Add support for debugging JITed code to ORC JIT from LLVM Kaleidoscope example☆13Jun 14, 2017Updated 8 years ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 2 years ago
- Verilog AST☆20Dec 2, 2023Updated 2 years ago
- CMurphi mirror: http://mclab.di.uniroma1.it/site/index.php/software/18-cmurphi☆12Jan 22, 2016Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆132May 19, 2022Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆72Dec 17, 2025Updated 3 months ago
- Docker image for writing environment for Japanese documents with LaTeX / TeX Live☆11Oct 29, 2023Updated 2 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 10 months ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago