Alternatives and similar repositories for PySysC

Users that are interested in PySysC are comparing it to the libraries listed below

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 9 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated 3 weeks ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• aolofsson / POSH
  ☆44Updated 5 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆46Updated 9 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated 3 weeks ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated this week
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆37Updated 3 weeks ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆45Updated 4 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆46Updated last week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆57Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 3 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆71Updated 10 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 2 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆61Updated 2 weeks ago