accellera-official / PySysC

Related projects ⓘ

Alternatives and complementary repositories for PySysC

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 3 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated 2 weeks ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆78Updated last month
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆35Updated 2 weeks ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆48Updated 3 weeks ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆21Updated last month
• aolofsson / POSH
  ☆39Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 3 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆22Updated 7 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆26Updated 6 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆52Updated 3 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆33Updated 7 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆36Updated 2 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 3 weeks ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆16Updated 11 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆42Updated last month
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆38Updated 4 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆21Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆31Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆62Updated 3 months ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated 9 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆63Updated 2 months ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆16Updated last year