Alternatives and similar repositories for PySysC

Users that are interested in PySysC are comparing it to the libraries listed below

• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆36Updated 2 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆28Updated 2 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 3 weeks ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 2 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆60Updated this week
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆53Updated 2 years ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated last week
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆37Updated last year
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆51Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 3 months ago