XedaHQ / xeda
Cross EDA Abstraction and Automation
☆36Updated this week
Alternatives and similar repositories for xeda:
Users that are interested in xeda are comparing it to the libraries listed below
- SystemVerilog FSM generator☆27Updated 8 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- ☆31Updated last year
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- ☆20Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated last month
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- IP-XACT XML binding library☆15Updated 8 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- An automatic clock gating utility☆43Updated 6 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Provides automation scripts for building BFMs☆16Updated 3 years ago
- SVA examples and demonstration☆16Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 10 months ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated last year
- YosysHQ SVA AXI Properties☆37Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 4 years ago
- SystemVerilog Linter based on pyslang☆25Updated 3 weeks ago
- SystemVerilog Logger☆17Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆50Updated last year
- 👾 Design ∪ Hardware☆73Updated 2 months ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆19Updated 4 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆22Updated 3 years ago