Cross EDA Abstraction and Automation
☆43Sep 18, 2026Updated this week
Alternatives and similar repositories for xeda
Users that are interested in xeda are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Sep 7, 2026Updated 2 weeks ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Development Package for the Hardware API for Lightweight Cryptography☆18Mar 27, 2025Updated last year
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- D3.js and ELK based schematic visualizer☆122May 13, 2026Updated 4 months ago
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- ☆30Oct 2, 2023Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- ☆15May 10, 2019Updated 7 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- LiteX Accelerator Block for GNU Radio☆24Feb 6, 2022Updated 4 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆69Dec 4, 2019Updated 6 years ago
- sample VCD files☆43Feb 13, 2026Updated 7 months ago
- FreeRTOS port for the RISC-V Virtual Prototype☆14Nov 9, 2020Updated 5 years ago
- 👾 Design ∪ Hardware☆79Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆91Apr 13, 2026Updated 5 months ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Tools for manipulating Fast Signal Trace (FST) format waveforms.☆18Oct 22, 2025Updated 11 months ago
- ☆114Dec 5, 2019Updated 6 years ago
- GUI editor for hardware description designs☆30Sep 14, 2026Updated last week
- ☆10Apr 8, 2021Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- ☆16Jan 25, 2026Updated 7 months ago
- An abstraction library for interfacing EDA tools☆796Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VHDL related news.☆27Updated this week
- ☆18Sep 2, 2020Updated 6 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Updated this week
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆18Aug 16, 2021Updated 5 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆332Jun 30, 2025Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year