Alternatives and similar repositories for xeda

Users that are interested in xeda are comparing it to the libraries listed below

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆43Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated 2 weeks ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆33Updated last year
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆44Updated 3 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆33Updated last month
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆54Updated 3 months ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated last week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 9 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 3 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆19Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 8 months ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆58Updated 5 months ago