XedaHQ / xedaLinks
Cross EDA Abstraction and Automation
☆40Updated 2 weeks ago
Alternatives and similar repositories for xeda
Users that are interested in xeda are comparing it to the libraries listed below
Sorting:
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆27Updated last month
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- ☆31Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- SystemVerilog FSM generator☆32Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Updated 4 years ago
- ☆20Updated 4 years ago
- Provides automation scripts for building BFMs☆16Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- UART cocotb module☆11Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated last year
- Python interface for cross-calling with HDL☆44Updated this week
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆19Updated 2 years ago
- IP-XACT XML binding library☆16Updated 9 years ago
- ☆33Updated 10 months ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆26Updated 5 months ago
- Running Python code in SystemVerilog☆71Updated 5 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Extended and external tests for Verilator testing☆17Updated 3 weeks ago