XedaHQ / xedaLinks
Cross EDA Abstraction and Automation
☆39Updated 3 weeks ago
Alternatives and similar repositories for xeda
Users that are interested in xeda are comparing it to the libraries listed below
Sorting:
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆25Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆31Updated last year
- SystemVerilog FSM generator☆32Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Provides automation scripts for building BFMs☆16Updated 4 months ago
- ☆32Updated 7 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- IP-XACT XML binding library☆16Updated 9 years ago
- Python library for operations with VCD and other digital wave files☆51Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆53Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated last month
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 6 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- CMake based hardware build system☆30Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Running Python code in SystemVerilog☆70Updated 2 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Import and export IP-XACT XML register models☆35Updated 2 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago