Alternatives and similar repositories for hdlparse:

Users that are interested in hdlparse are comparing it to the libraries listed below

• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆109Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 weeks ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 4 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆61Updated 4 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆52Updated 4 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆44Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆108Updated last year
• accellera / uvm
  ☆45Updated 8 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆51Updated 5 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 7 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆59Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated this week
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago