Alternatives and similar repositories for hdlparse

Users that are interested in hdlparse are comparing it to the libraries listed below

• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 2 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆67Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆137Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 3 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated 2 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last month
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆61Updated last week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆63Updated 8 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆35Updated 2 weeks ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated 11 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆62Updated 4 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆50Updated this week
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆194Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆111Updated 4 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆59Updated 2 weeks ago