Simple parser for extracting VHDL documentation
☆73Jul 12, 2024Updated last year
Alternatives and similar repositories for hdlparse
Users that are interested in hdlparse are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆323Jun 30, 2025Updated 10 months ago
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆24Mar 1, 2024Updated 2 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆26Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Protocol decode and synthesis library☆70Feb 7, 2019Updated 7 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- VHDL grammar for tree-sitter☆32Dec 20, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Exploration of alternative hardware description languages☆28Mar 9, 2018Updated 8 years ago
- Style guide enforcement for VHDL☆238Updated this week
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 5 months ago
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆789Jun 15, 2024Updated last year
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- A JSON library implemented in VHDL.☆84Feb 8, 2026Updated 2 months ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 5 years ago
- Open PicoBlaze Assembler☆63Oct 29, 2023Updated 2 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆81Mar 6, 2019Updated 7 years ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- cocotb: Python-based chip (RTL) verification☆2,354Apr 27, 2026Updated last week
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆37Dec 24, 2020Updated 5 years ago
- ☆27Mar 17, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Unit testing for cocotb☆169Apr 18, 2026Updated 2 weeks ago
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- VHDL plugin for RgGen☆15Apr 19, 2026Updated 2 weeks ago
- SystemVerilog compiler and language services☆1,027Updated this week
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 13 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- An abstraction library for interfacing EDA tools☆762Apr 24, 2026Updated last week