Alternatives and similar repositories for hdlparse

Users that are interested in hdlparse are comparing it to the libraries listed below

• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated 2 weeks ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 5 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 5 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆66Updated 9 months ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆57Updated 10 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• kevinpt / symbolator
  HDL symbol generator
  ☆190Updated 2 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 3 weeks ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆61Updated 2 weeks ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆54Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆71Updated 10 months ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated 8 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated 3 weeks ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆67Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆60Updated 5 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated 3 weeks ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆151Updated 4 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week