Alternatives and similar repositories for boa-risc-v

Users that are interested in boa-risc-v are comparing it to the libraries listed below

• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated last week
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆28Updated 2 months ago
• pulp-platform / RVfplib
  Optimized RISC-V FP emulation for 32-bit processors
  ☆36Updated 4 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated 11 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆26Updated 2 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 3 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated last year
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆99Updated 6 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆90Updated last month
• olofk / qerv
  ☆18Updated 6 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆57Updated last week
• antmicro / virtex-ultrascale-pcie
  ☆15Updated 2 years ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆19Updated 7 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 4 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 4 months ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆32Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆49Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• AlSaqr-platform / he-soc
  ☆32Updated 3 weeks ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated last week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆38Updated 3 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago