Alternatives and similar repositories for BluespecIntroGuide

Users that are interested in BluespecIntroGuide are comparing it to the libraries listed below

• ucsc-vama / essent
  high-performance RTL simulator
  ☆174Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆155Updated 9 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆105Updated 3 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆108Updated 9 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• lana555 / dynamatic
  ☆87Updated last year
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆111Updated 3 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆161Updated 5 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆88Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 3 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆125Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• ucb-bar / sha3
  ☆81Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆60Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆109Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆48Updated 10 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆126Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated last week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago