kcamenzind / BluespecIntroGuideLinks
An introductory guide to Bluespec (BSV)
☆66Updated 6 years ago
Alternatives and similar repositories for BluespecIntroGuide
Users that are interested in BluespecIntroGuide are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆184Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆114Updated 2 months ago
- A dynamic verification library for Chisel.☆159Updated last year
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- ☆87Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Main page☆129Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- Python wrapper for verilator model☆92Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated 3 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆82Updated last year
- Floating point modules for CHISEL☆32Updated 11 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 6 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- chipyard in mill :P☆77Updated 2 years ago
- RISC-V Formal Verification Framework☆175Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year