kcamenzind / BluespecIntroGuideLinks
An introductory guide to Bluespec (BSV)
☆66Updated 6 years ago
Alternatives and similar repositories for BluespecIntroGuide
Users that are interested in BluespecIntroGuide are comparing it to the libraries listed below
Sorting:
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆111Updated 3 weeks ago
- high-performance RTL simulator☆182Updated last year
- A dynamic verification library for Chisel.☆158Updated last year
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- Python wrapper for verilator model☆92Updated last year
- ☆87Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- The Task Parallel System Composer (TaPaSCo)☆113Updated last week
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- RISC-V Formal Verification Framework☆167Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Main page☆128Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- A tool for synthesizing Verilog programs☆107Updated 3 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆147Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 6 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆52Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆94Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- chipyard in mill :P☆77Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- Equivalence checking with Yosys☆51Updated 2 weeks ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 10 months ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- ☆104Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆165Updated 5 years ago