kcamenzind / BluespecIntroGuideLinks
An introductory guide to Bluespec (BSV)
☆62Updated 6 years ago
Alternatives and similar repositories for BluespecIntroGuide
Users that are interested in BluespecIntroGuide are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆168Updated last year
- Bluespec BSV HLHDL tutorial☆105Updated 9 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆101Updated 2 months ago
- ☆86Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A dynamic verification library for Chisel.☆152Updated 8 months ago
- Python wrapper for verilator model☆86Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆112Updated last year
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- Main page☆126Updated 5 years ago
- RISC-V Virtual Prototype☆172Updated 7 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- (System)Verilog to Chisel translator☆115Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated 2 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆46Updated 8 months ago
- RISC-V Formal Verification Framework☆142Updated last month
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- A hardware synthesis framework with multi-level paradigm☆40Updated 6 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- ☆81Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆122Updated last week
- ☆103Updated 3 years ago
- PACoGen: Posit Arithmetic Core Generator☆73Updated 5 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆84Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆188Updated last month