kcamenzind / BluespecIntroGuideLinks
An introductory guide to Bluespec (BSV)
☆66Updated 6 years ago
Alternatives and similar repositories for BluespecIntroGuide
Users that are interested in BluespecIntroGuide are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆186Updated last year
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- A dynamic verification library for Chisel.☆160Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆119Updated 3 months ago
- Python wrapper for verilator model☆93Updated 2 years ago
- ☆87Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- ☆82Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 9 months ago
- RISC-V Formal Verification Framework☆178Updated 3 weeks ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated this week
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- RISC-V Virtual Prototype☆183Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Main page☆129Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆56Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆62Updated 7 months ago
- The OpenPiton Platform☆28Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- RISC-V Torture Test☆212Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- Next generation CGRA generator☆118Updated last week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago