bluespec / AWSteria_InfraLinks
"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
☆19Updated last year
Alternatives and similar repositories for AWSteria_Infra
Users that are interested in AWSteria_Infra are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- Miscellaneous components for bluespec☆11Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Intel Compiler for SystemC☆26Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 2 weeks ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Updated 3 years ago
- Hardware generator debugger☆77Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- An implementation of RISC-V☆46Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- ☆59Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆41Updated 2 weeks ago
- The Task Parallel System Composer (TaPaSCo)☆115Updated this week
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated last month
- ☆37Updated last year
- Useful utilities for BAR projects☆32Updated last year
- Chisel Cheatsheet☆34Updated 2 years ago
- ☆12Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- A SystemVerilog source file pickler.☆60Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- high-performance RTL simulator☆184Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 4 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago