bluespec / AWSteria_Infra
"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
☆18Updated last month
Related projects ⓘ
Alternatives and complementary repositories for AWSteria_Infra
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated 9 months ago
- SystemVerilog FSM generator☆26Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- The specification for the FIRRTL language☆46Updated this week
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- Useful utilities for BAR projects☆30Updated 10 months ago
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- Equivalence checking with Yosys☆31Updated 2 weeks ago
- ☆52Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- ☆36Updated 2 years ago
- ☆31Updated last month
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- ☆20Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- Intel Compiler for SystemC☆23Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- SystemVerilog frontend for Yosys☆46Updated this week
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- A prototype GUI for chisel-development☆52Updated 4 years ago
- Chisel HDL example applications☆30Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Pure digital components of a UCIe controller☆48Updated 2 weeks ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆23Updated 3 weeks ago