bluespec / AWSteria_Infra

Related projects: ⓘ

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆35Updated 2 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 7 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆66Updated 4 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆28Updated 6 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆55Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated last month
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆74Updated 3 weeks ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 11 months ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆23Updated 7 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆49Updated 9 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆48Updated 8 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆39Updated 2 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆33Updated 3 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆25Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆41Updated last week
• pulp-platform / axi_llc
  ☆17Updated last week
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆29Updated 2 years ago
• grebe / ofdm
  Chisel Things for OFDM
  ☆30Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆39Updated last week
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆28Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆26Updated last month