HDL libraries and projects
☆1,945Jun 11, 2026Updated this week
Alternatives and similar repositories for hdl
Users that are interested in hdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Ethernet components for FPGA implementation☆2,982Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,071Feb 27, 2025Updated last year
- Must-have verilog systemverilog modules☆1,973Mar 12, 2026Updated 3 months ago
- Verilog library for ASIC and FPGA designers☆1,421May 8, 2024Updated 2 years ago
- Verilog PCI express components☆1,610Apr 26, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Software drivers in C for systems without an operating system☆1,358Jun 8, 2026Updated last week
- Linux kernel variant from Analog Devices; see README.md for details☆630Updated this week
- Various HDL (Verilog) IP Cores☆908Jul 1, 2021Updated 4 years ago
- Verilog AXI stream components for FPGA implementation☆893Feb 27, 2025Updated last year
- open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware☆865Sep 23, 2025Updated 8 months ago
- The RIFFA development repository☆875Jun 11, 2024Updated 2 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆93Sep 12, 2018Updated 7 years ago
- A huge VHDL library for FPGA and digital ASIC development☆464Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆686Dec 31, 2025Updated 5 months ago
- Open source FPGA-based NIC and platform for in-network compute☆2,358Jul 5, 2024Updated last year
- The official Linux kernel from Xilinx☆1,548Jun 8, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,203Jun 27, 2024Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆623Mar 15, 2018Updated 8 years ago
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆472Jan 29, 2023Updated 3 years ago
- An Open-source FPGA IP Generator☆1,114Updated this week
- A small, light weight, RISC CPU soft core☆1,550Dec 8, 2025Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software☆4,652May 21, 2026Updated 3 weeks ago
- A cross platform library for interfacing with local and remote Linux IIO devices☆618Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,420Updated this week
- PlutoSDR Firmware☆451Apr 23, 2026Updated last month
- Xilinx Tcl Store☆374Jun 2, 2026Updated last week
- A GTK+ based oscilloscope application for interfacing with various IIO devices☆335May 15, 2026Updated last month
- Build your hardware, easily!☆3,927Updated this week
- Hardware Description Languages☆1,151Apr 6, 2026Updated 2 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,568May 12, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆606Jul 30, 2025Updated 10 months ago
- Small footprint and configurable PCIe core☆704Jun 4, 2026Updated last week
- Scala based HDL☆2,000Updated this week
- Testbenches for HDL projects☆23Updated this week
- Verilog I2C interface for FPGA implementation☆701Feb 27, 2025Updated last year
- Bus bridges and other odds and ends☆679Jun 2, 2026Updated last week
- Common SystemVerilog components☆757Jun 5, 2026Updated last week