laforest / FPGADesignElementsLinks
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
☆446Updated last year
Alternatives and similar repositories for FPGADesignElements
Users that are interested in FPGADesignElements are comparing it to the libraries listed below
Sorting:
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆724Updated 7 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆676Updated this week
- Bus bridges and other odds and ends☆587Updated 4 months ago
- A simple, basic, formally verified UART controller☆309Updated last year
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- A huge VHDL library for FPGA and digital ASIC development☆396Updated last week
- Small footprint and configurable DRAM core☆434Updated 2 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆517Updated 2 years ago
- Multi-platform nightly builds of open source FPGA tools☆299Updated 3 years ago
- An abstraction library for interfacing EDA tools☆710Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆602Updated last month
- Opensource DDR3 Controller☆381Updated 3 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆509Updated 3 years ago
- Example designs showing different ways to use F4PGA toolchains.☆277Updated last year
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆588Updated last month
- SystemVerilog to Verilog conversion☆663Updated 2 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆293Updated this week
- A Verilog implementation of DisplayPort protocol for FPGAs☆256Updated 6 years ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆406Updated last week
- A list of resources related to the open-source FPGA projects☆425Updated 2 years ago
- lowRISC Style Guides☆453Updated 3 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆406Updated last week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆346Updated 6 months ago
- Small footprint and configurable PCIe core☆583Updated last week
- Common SystemVerilog components☆654Updated last week
- FOSS Flow For FPGA☆405Updated 8 months ago
- ☆343Updated 2 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆640Updated last week
- LiteX boards files☆427Updated this week
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆281Updated 4 years ago