Alternatives and similar repositories for wb2axip

Users that are interested in wb2axip are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆630Updated 2 weeks ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆461Updated 3 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆806Updated 3 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,286Updated last week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆349Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆497Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆261Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated 2 weeks ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆798Updated 3 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆384Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆487Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆333Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆401Updated 11 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆236Updated this week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆320Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆690Updated 3 weeks ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆612Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆428Updated 8 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆325Updated 11 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆324Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆399Updated 3 weeks ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆432Updated 8 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆455Updated 2 weeks ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆414Updated last week