Alternatives and similar repositories for wb2axip:

Users that are interested in wb2axip are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆599Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆795Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,252Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆567Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆436Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆322Updated 11 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆600Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆422Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆418Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆475Updated 2 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆252Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆615Updated last week
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆382Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆419Updated 7 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆474Updated last month
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆313Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆313Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆774Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆298Updated last year
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆394Updated this week
• Xilinx / XilinxBoardStore
  ☆285Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆681Updated last week
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆394Updated 9 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆310Updated 3 weeks ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆354Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆443Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆273Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆521Updated this week