Alternatives and similar repositories for wb2axip

Users that are interested in wb2axip are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆645Updated 2 weeks ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆492Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆585Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆510Updated 5 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆429Updated last month
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆354Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆812Updated 4 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,319Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆436Updated last week
• alexforencich / verilog-uart
  Verilog UART
  ☆493Updated 4 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated last week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆581Updated 4 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆625Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆818Updated 4 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆283Updated 3 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆503Updated 7 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆657Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆362Updated 3 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆699Updated 3 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆327Updated this week
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆335Updated 8 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆403Updated last month