Alternatives and similar repositories for verilog:

Users that are interested in verilog are comparing it to the libraries listed below

• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆802Updated 2 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆779Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆480Updated 2 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,267Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆604Updated 2 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,700Updated 2 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,279Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 3 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,279Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆552Updated 3 weeks ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆419Updated 2 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆330Updated last year
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆445Updated 3 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆624Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆425Updated 7 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆397Updated 3 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,005Updated 3 years ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆465Updated 2 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆826Updated 10 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,063Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆621Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated last week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆612Updated last month
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆528Updated 3 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆651Updated 5 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆423Updated 3 weeks ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,763Updated last month
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆355Updated this week