Alternatives and similar repositories for verilog

Users that are interested in verilog are comparing it to the libraries listed below

• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆839Updated 4 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆506Updated 7 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆833Updated 7 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,385Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆648Updated 7 months ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆433Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆593Updated 6 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆679Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,122Updated 4 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,831Updated 7 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆387Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,341Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆525Updated 4 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,446Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated 3 weeks ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆571Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆673Updated 3 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,859Updated 2 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆596Updated 2 months ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆348Updated 8 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆444Updated 5 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆612Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,106Updated 4 years ago
• Digilent / vivado-boards
  ☆468Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆460Updated 4 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆527Updated 2 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated 2 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆464Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆936Updated 11 months ago