Alternatives and similar repositories for verilog

Users that are interested in verilog are comparing it to the libraries listed below

• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆842Updated 4 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆511Updated 8 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆838Updated 8 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆655Updated 8 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,397Updated 2 weeks ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆684Updated 2 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,841Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆602Updated 6 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,349Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆386Updated last month
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆435Updated 3 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,449Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,136Updated 5 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆939Updated 11 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆575Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated 3 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,121Updated 4 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,011Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆671Updated last week
• Digilent / vivado-library
  ☆646Updated 3 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 5 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆595Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆519Updated 11 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆459Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆613Updated this week
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated last week
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆536Updated 2 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆348Updated 8 years ago