Repository for basic (and not so basic) Verilog blocks with high re-use potential
☆619Mar 15, 2018Updated 8 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆861Apr 15, 2020Updated 6 years ago
- Various HDL (Verilog) IP Cores☆897Jul 1, 2021Updated 4 years ago
- Verilog Ethernet components for FPGA implementation☆2,947Feb 27, 2025Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆68Dec 4, 2019Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Verilog UART☆561Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,037Feb 27, 2025Updated last year
- HDL libraries and projects☆1,913Updated this week
- Icarus Verilog☆3,434Updated this week
- training labs and examples☆461Aug 1, 2022Updated 3 years ago
- MIPS CPU implemented in Verilog☆646Oct 3, 2017Updated 8 years ago
- Verilog I2C interface for FPGA implementation☆698Feb 27, 2025Updated last year
- A collection of demonstration digital filters☆171Jan 18, 2024Updated 2 years ago
- Verilog PCI express components☆1,591Apr 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Pi emulating a GameBoy sounds cheap. What about an FPGA?☆521Dec 10, 2022Updated 3 years ago
- Verilog AXI stream components for FPGA implementation☆886Feb 27, 2025Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 8 months ago
- A small, light weight, RISC CPU soft core☆1,532Dec 8, 2025Updated 4 months ago
- Collection of open-source peripherals in Verilog☆185May 3, 2022Updated 4 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆12Aug 6, 2025Updated 9 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,546Apr 27, 2026Updated last week
- Common SystemVerilog components☆738Apr 27, 2026Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆687Jul 16, 2025Updated 9 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,127Jun 27, 2024Updated last year
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆604Jul 30, 2025Updated 9 months ago
- Verilog SDRAM memory controller☆368May 13, 2017Updated 8 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆325Mar 8, 2026Updated last month
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- FPGA raycaster engine written in verilog☆13Apr 19, 2019Updated 7 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,226Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆589Oct 10, 2021Updated 4 years ago
- Mathematical Functions in Verilog☆98Mar 7, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog wishbone components☆127Jan 5, 2024Updated 2 years ago
- Implementation of CNN using Verilog☆246Oct 13, 2017Updated 8 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆660Apr 29, 2026Updated last week
- An open source library for image processing on FPGA.☆632Jun 16, 2015Updated 10 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,413Feb 13, 2026Updated 2 months ago