Alternatives and similar repositories for riscv-vp

Users that are interested in riscv-vp are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated 3 weeks ago
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆258Updated 5 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆123Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆112Updated this week
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆172Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated 11 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆123Updated last week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆142Updated last year
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆329Updated this week
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆232Updated 2 weeks ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆186Updated last month
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆92Updated this week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆154Updated 5 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆157Updated last year
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆123Updated 2 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆298Updated 2 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆219Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆122Updated 4 months ago