Alternatives and similar repositories for riscv-vp

Users that are interested in riscv-vp are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆162Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆99Updated 2 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆71Updated last month
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆141Updated 5 years ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆110Updated this week
• chipsalliance / VeeR-ISS
  ☆141Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆150Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 8 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 3 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆171Updated 2 weeks ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• subbdue / systemverilog.io
  Code used in
  ☆193Updated 8 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆196Updated last week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆122Updated 4 years ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆314Updated 7 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆183Updated last week