Alternatives and similar repositories for betrusted-soc

Users that are interested in betrusted-soc are comparing it to the libraries listed below

• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆111Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• tenstorrent / rv-core-dv-kit
  ☆26Updated 9 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 7 months ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆72Updated 11 years ago
• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated 7 months ago
• PSPReverse / PSPTrace
  correlate an SPI capture of an AMD boot procedure to the PSP firmware components
  ☆16Updated last week
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆51Updated 6 months ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 2 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆89Updated 6 years ago
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆39Updated last year
• SymbiFlow / nextpnr
  nextpnr portable FPGA place and route tool
  ☆20Updated last year
• teknohog / rautanoppa
  Hardware random number generator for FPGAs
  ☆10Updated 10 years ago
• himanshu5-prog / vortexGPU
  ☆22Updated 4 years ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆63Updated 5 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 7 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆64Updated 6 years ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated 2 months ago