sutajiokousagi / betrusted-socLinks
betrusted.io main SoC design
☆14Updated 5 years ago
Alternatives and similar repositories for betrusted-soc
Users that are interested in betrusted-soc are comparing it to the libraries listed below
Sorting:
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated last week
- PCIe analyzer experiments☆62Updated 5 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 5 years ago
- Demo SoC for SiliconCompiler.☆61Updated last week
- ☆25Updated 7 months ago
- RISC-V Configuration Structure☆41Updated 11 months ago
- IRSIM switch-level simulator for digital circuits☆34Updated 6 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- ☆22Updated 4 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆49Updated 5 months ago
- Waveform Generator☆11Updated 3 years ago
- Industry standard I/O for Amaranth HDL☆29Updated last year
- An open-source custom cache generator.☆34Updated last year
- PicoRV☆43Updated 5 years ago
- nextpnr portable FPGA place and route tool☆20Updated last year
- OpenSPARC-based SoC☆70Updated 11 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- IP submodules, formatted for easier CI integration☆30Updated 3 weeks ago
- Exploring gate level simulation☆58Updated 5 months ago
- Small footprint and configurable Inter-Chip communication cores☆65Updated 2 weeks ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- ☆18Updated 5 years ago
- Betrusted embedded controller (UP5K)☆48Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Updated 3 years ago
- System on Chip toolkit for Amaranth HDL☆93Updated last year
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago