jeras / rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
☆11Updated last year
Related projects ⓘ
Alternatives and complementary repositories for rp32
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆12Updated 2 years ago
- USB virtual model in C++ for Verilog☆28Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- A padring generator for ASICs☆22Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Wishbone interconnect utilities☆37Updated 5 months ago
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- ☆12Updated 3 years ago
- Master-thesis-final☆18Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- ☆9Updated last year
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- JTAG DPI module for OpenRISC simulation with Verilator☆16Updated 12 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Harmon Instruments FIFO to PCI Express interface☆11Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Virtual development board for HDL design☆39Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆14Updated 8 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆39Updated 3 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆25Updated 3 years ago
- Library of reusable VHDL components☆25Updated 8 months ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆48Updated last week