jeras / rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
☆12Updated last year
Alternatives and similar repositories for rp32:
Users that are interested in rp32 are comparing it to the libraries listed below
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Master-thesis-final☆18Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Wishbone interconnect utilities☆38Updated 8 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Use ECP5 JTAG port to interact with user design☆26Updated 3 years ago
- Harmon Instruments FIFO to PCI Express interface☆11Updated 3 years ago
- Repo to help explain the different options users have for packaging.☆16Updated 2 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆28Updated last month
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- USB virtual model in C++ for Verilog☆29Updated 3 months ago
- Tiny tips for Colorlight i5 FPGA board☆56Updated 3 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆20Updated last year
- ☆15Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Miscellaneous ULX3S examples (advanced)☆75Updated last week
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆20Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- FPGA board-level debugging and reverse-engineering tool☆33Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago