jeras / rp32Links
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
☆20Updated 3 weeks ago
Alternatives and similar repositories for rp32
Users that are interested in rp32 are comparing it to the libraries listed below
Sorting:
- A Risc-V SoC for Tiny Tapeout☆43Updated 2 weeks ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated last week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 11 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated this week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- Wishbone interconnect utilities☆43Updated 10 months ago
- RISC-V Nox core☆70Updated 4 months ago
- ☆14Updated 8 months ago
- Experimental flows using nextpnr for Xilinx devices☆53Updated 3 weeks ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆74Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆73Updated this week
- Bitstream relocation and manipulation tool.