Alternatives and similar repositories for wildcat

Users that are interested in wildcat are comparing it to the libraries listed below

• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated 2 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated 10 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆52Updated 5 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 10 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆178Updated this week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆110Updated 4 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆113Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆42Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆161Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆150Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 2 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated 3 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆69Updated 9 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆65Updated last week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆63Updated last week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago