schoeberl / wildcat
An implementation of RISC-V
☆20Updated this week
Alternatives and similar repositories for wildcat:
Users that are interested in wildcat are comparing it to the libraries listed below
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 2 months ago
- Docker Development Environment for SpinalHDL☆18Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- ☆63Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Chisel Cheatsheet☆32Updated last year
- Platform Level Interrupt Controller☆35Updated 8 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- ☆41Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Advanced Debug Interface☆12Updated last year
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- ☆35Updated 11 months ago
- FPGA optimized RISC-V (RV32IM) implemenation☆33Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Lipsi: Probably the Smallest Processor in the World☆82Updated 9 months ago
- ☆36Updated 2 years ago
- ☆26Updated 3 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆51Updated last month
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- Xilinx Unisim Library in Verilog☆72Updated 4 years ago
- A Verilog Synthesis Regression Test☆35Updated 9 months ago
- ☆17Updated 2 years ago