riktw / SoftcoreComparisons
The code for an FPGA softcore comparison
☆11Updated 4 years ago
Alternatives and similar repositories for SoftcoreComparisons
Users that are interested in SoftcoreComparisons are comparing it to the libraries listed below
Sorting:
- Virtual development board for HDL design☆42Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).☆21Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 4 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- PicoRV☆44Updated 5 years ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Small footprint and configurable SPI core☆41Updated 3 weeks ago
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆15Updated 3 weeks ago
- sample VCD files☆37Updated last year
- ☆22Updated 3 years ago
- ☆20Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Library of reusable VHDL components☆28Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago