riktw / SoftcoreComparisonsLinks
The code for an FPGA softcore comparison
☆11Updated 5 years ago
Alternatives and similar repositories for SoftcoreComparisons
Users that are interested in SoftcoreComparisons are comparing it to the libraries listed below
Sorting:
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).☆21Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- Virtual development board for HDL design☆42Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- Spen's Official OpenOCD Mirror☆50Updated 3 months ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Nitro USB FPGA core☆85Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last month
- PicoRV☆44Updated 5 years ago
- ☆12Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆48Updated 2 weeks ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆18Updated this week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆55Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- USB DFU bootloader gateware / firmware for FPGAs☆65Updated 8 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated 3 weeks ago
- Library of reusable VHDL components☆28Updated last year
- sample VCD files☆37Updated last year