riktw / SoftcoreComparisonsLinks
The code for an FPGA softcore comparison
☆11Updated 5 years ago
Alternatives and similar repositories for SoftcoreComparisons
Users that are interested in SoftcoreComparisons are comparing it to the libraries listed below
Sorting:
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- Nitro USB FPGA core☆86Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Virtual Development Board☆64Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Ultimate ECP5 development board☆116Updated 6 years ago
- CoreScore☆172Updated 2 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Wishbone interconnect utilities☆44Updated last month
- ☆72Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Updated 7 months ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- A padring generator for ASICs☆25Updated 2 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- Project X-Ray Database: XC7 Series☆74Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆27Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Using the TinyFPGA BX USB code in user designs☆52Updated 7 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- VHDL library 4 FPGAs☆185Updated this week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago