Alternatives and similar repositories for riscv_fpga

Users that are interested in riscv_fpga are comparing it to the libraries listed below

• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆18Updated 4 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆16Updated 2 years ago
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆17Updated 5 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆30Updated 6 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆55Updated last year
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆15Updated 4 years ago
• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆20Updated 2 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆28Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆20Updated 4 years ago
• lawrie / blackicemxbook
  ☆26Updated 5 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 6 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆42Updated last year
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆32Updated 8 years ago
• michg / pyocdriscv32
  Python script for controlling the debug-jtag port of riscv cores
  ☆14Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆45Updated 4 months ago
• rschlaikjer / fpga-3-softcores
  Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
  ☆13Updated 4 years ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆21Updated 7 months ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆16Updated last year
• OldRepoPreservation / mpeg2fpga
  An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.
  ☆25Updated 6 years ago
• TinyTapeout / tinytapeout-03
  ☆16Updated last year
• tomverbeure / usb_system
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Updated 3 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆27Updated 3 years ago
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆18Updated this week