Alternatives and similar repositories for quasiSoC

Users that are interested in quasiSoC are comparing it to the libraries listed below

• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated last month
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆105Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated this week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 10 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated last week
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆187Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆134Updated 7 years ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆112Updated last year
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆252Updated 3 months ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆171Updated 4 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆114Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆253Updated last year
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• sipeed / TangMega-138KPro-example
  Tang Mega 138K Pro examples
  ☆96Updated 5 months ago
• evantandersen / fpga-gpu
  A basic GPU for altera FPGAs
  ☆88Updated 6 years ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆92Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated last week
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆77Updated 2 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆91Updated 7 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated 2 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago