regymm / quasiSoCLinks
Linux capable RISC-V SoC designed to be readable and useful.
☆147Updated 3 weeks ago
Alternatives and similar repositories for quasiSoC
Users that are interested in quasiSoC are comparing it to the libraries listed below
Sorting:
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆163Updated last week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆105Updated 11 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆214Updated last month
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 7 months ago
- Doom classic port to lightweight RISC‑V☆94Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆94Updated last week
- 64-bit multicore Linux-capable RISC-V processor☆94Updated last month
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆172Updated last year
- Experimental flows using nextpnr for Xilinx devices☆240Updated 8 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- A Video display simulator☆170Updated last month
- ☆289Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆92Updated last week
- SystemVerilog synthesis tool☆196Updated 3 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆79Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆84Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆177Updated this week
- 10Gb Ethernet Switch☆218Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆101Updated last month
- Verilog implementation of a RISC-V core☆118Updated 6 years ago
- CORE-V Family of RISC-V Cores☆274Updated 4 months ago
- Example LED blinking project for your FPGA dev board of choice☆177Updated 3 weeks ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆294Updated last month