regymm / quasiSoCLinks
Linux capable RISC-V SoC designed to be readable and useful.
☆151Updated 2 months ago
Alternatives and similar repositories for quasiSoC
Users that are interested in quasiSoC are comparing it to the libraries listed below
Sorting:
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆168Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆147Updated 9 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- 10Gb Ethernet Switch☆225Updated 3 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 8 months ago
- 64-bit multicore Linux-capable RISC-V processor☆93Updated 3 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆175Updated last year
- CoreScore☆159Updated 6 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A Video display simulator☆171Updated 2 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated last year
- RISC-V Nox core☆66Updated last week
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆72Updated this week
- Example LED blinking project for your FPGA dev board of choice☆179Updated 2 months ago
- Dual-issue RV64IM processor for fun & learning☆63Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆240Updated 8 months ago
- 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.☆104Updated 5 months ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆86Updated 4 years ago
- Verilog implementation of a RISC-V core☆122Updated 6 years ago
- 😎 A curated list of awesome RISC-V implementations☆137Updated 2 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆88Updated last month
- Simple 8-bit UART realization on Verilog HDL.☆108Updated last year
- A pipelined RISC-V processor☆57Updated last year
- ☆293Updated 3 weeks ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 3 months ago