Linux capable RISC-V SoC designed to be readable and useful.
☆159Dec 19, 2025Updated 2 months ago
Alternatives and similar repositories for quasiSoC
Users that are interested in quasiSoC are comparing it to the libraries listed below
Sorting:
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Feb 25, 2026Updated last week
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆224Feb 19, 2026Updated 2 weeks ago
- FLIX-V: FPGA, Linux and RISC-V☆42Nov 5, 2023Updated 2 years ago
- buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"☆26Apr 23, 2024Updated last year
- RISC-V XV6/Linux SoC, marchID: 0x2b☆1,069Mar 3, 2026Updated last week
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Feb 3, 2026Updated last month
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- My self-designed ZYNQ-7010 4-layer developement board.☆35Jul 25, 2021Updated 4 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Jun 21, 2023Updated 2 years ago
- Simple risc-v emulator, able to run linux, written in C.☆148Apr 11, 2024Updated last year
- A tiny C header-only risc-v emulator.☆2,067Dec 21, 2025Updated 2 months ago
- Doom classic port to lightweight RISC‑V☆107Jul 25, 2022Updated 3 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆496Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆321Updated this week
- ☆33Nov 25, 2022Updated 3 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 3 months ago
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆60Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Feb 2, 2026Updated last month
- Opensource DDR3 Controller☆420Jan 18, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated last month
- RISC-V 64 CPU☆10Oct 4, 2025Updated 5 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- Run Linux on MCUs such as ESP32C3 with RISC-V emulator☆127Apr 4, 2024Updated last year
- A pipelined RISC-V processor☆63Dec 1, 2023Updated 2 years ago
- Another size-optimized RISC-V CPU for your consideration.☆60Mar 1, 2026Updated last week
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆156Mar 22, 2025Updated 11 months ago
- ☆309Jan 23, 2026Updated last month
- 3-stage RV32IMACZb* processor with debug☆1,012Dec 14, 2025Updated 2 months ago
- TinyGPUs, making graphics hardware for 1990s games☆168Jan 24, 2026Updated last month
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Description of a RISC-V architecture based on MIPS 3000☆13Apr 24, 2023Updated 2 years ago
- Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignore…☆10Updated this week
- GSI Timing Gateware and Tools☆14Feb 25, 2026Updated last week
- A Risc-V SoC for Tiny Tapeout☆49Dec 2, 2025Updated 3 months ago