regymm / quasiSoC
Linux capable RISC-V SoC designed to be readable and useful.
☆138Updated 4 months ago
Alternatives and similar repositories for quasiSoC:
Users that are interested in quasiSoC are comparing it to the libraries listed below
- Naive Educational RISC V processor☆78Updated 4 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆144Updated this week
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 3 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆87Updated 5 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆101Updated 8 months ago
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 10 months ago
- A simple RISC V core for teaching☆176Updated 3 years ago
- ☆275Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆94Updated 7 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- RISC-V Formal Verification Framework☆127Updated last month
- Tang Mega 138K Pro examples☆66Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆142Updated 3 months ago
- RISC-V Nox core☆62Updated 6 months ago
- A pipelined RISC-V processor☆50Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆93Updated 3 years ago
- CORE-V Family of RISC-V Cores☆231Updated last week
- Example LED blinking project for your FPGA dev board of choice☆170Updated 2 months ago
- A Video display simulator☆161Updated 7 months ago
- Experimental flows using nextpnr for Xilinx devices☆225Updated 4 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆161Updated 11 months ago
- 64-bit multicore Linux-capable RISC-V processor☆84Updated 5 months ago
- 10Gb Ethernet Switch☆170Updated 11 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆205Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆310Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆96Updated 2 years ago