regymm / quasiSoC
Linux capable RISC-V SoC designed to be readable and useful.
☆142Updated 5 months ago
Alternatives and similar repositories for quasiSoC:
Users that are interested in quasiSoC are comparing it to the libraries listed below
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆150Updated 2 weeks ago
- Naive Educational RISC V processor☆79Updated 6 months ago
- ☆280Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆89Updated 3 weeks ago
- CORE-V Family of RISC-V Cores☆252Updated 2 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated last week
- SoC based on VexRiscv and ICE40 UP5K☆156Updated 3 weeks ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 5 months ago
- RISC-V Formal Verification Framework☆131Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 5 months ago
- 10Gb Ethernet Switch☆180Updated 3 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆96Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆103Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆89Updated 7 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆208Updated this week
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆102Updated 8 months ago
- RISC-V Verification Interface☆87Updated last month
- Verilog implementation of a RISC-V core☆113Updated 6 years ago
- RISC-V Nox core☆62Updated 3 weeks ago
- Example LED blinking project for your FPGA dev board of choice☆174Updated last month
- Opensource DDR3 Controller☆310Updated 3 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆335Updated this week
- A Video display simulator☆164Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 8 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆166Updated last year
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- Tang Mega 138K Pro examples☆68Updated 4 months ago