A template-based, layer-oriented High Level Synthesis Tool for AI algorithms
☆15Jul 20, 2026Updated 3 months ago
Alternatives and similar repositories for tinyHLS
Users that are interested in tinyHLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rust support for the open-source NEORV32 RISC-V microcontroller.☆14Feb 19, 2026Updated 8 months ago
- RISC-V Double Trap Fast-Track Extension☆15Mar 10, 2026Updated 7 months ago
- The ISA specification for the ZiCondOps extension.☆18Mar 21, 2024Updated 2 years ago
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Apr 16, 2026Updated 6 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆107Jun 24, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Scalable Interface for RISC-V ISA Extensions☆26Aug 13, 2026Updated 2 months ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated 2 years ago
- This repo contains the code developed for my master thesis☆13Mar 24, 2022Updated 4 years ago
- An inhouse RISC-V 32-bits CPU☆22Oct 21, 2026Updated last week
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 5 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated 3 weeks ago
- A proof-of-concept (hack) to implement neural network inference on a very tiny 8-bit microcontroller.☆76May 5, 2024Updated 2 years ago
- My Slides☆17Jun 10, 2025Updated last year
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆21Apr 7, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 9 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Sep 28, 2026Updated last month
- Documentation of YADAN, a RISC-V Core, SoC, and Board. Designed for engineering education. // 鸭蛋的文档。☆16Jun 9, 2026Updated 4 months ago
- Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr☆27Jun 14, 2020Updated 6 years ago
- My ~/.vim☆19Updated this week
- ☆13Jul 14, 2025Updated last year
- The VE-HEP RTL and Firmware☆12Mar 19, 2024Updated 2 years ago
- Ada-language framework☆53Updated this week
- ☆16Mar 9, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A ROHD-based framework for connectivity and assembly of hardware designs.☆14Sep 9, 2026Updated last month
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Updated this week
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- ☆13Oct 18, 2023Updated 3 years ago
- On-Device Learning for Low-Power IoT Devices☆15Aug 12, 2023Updated 3 years ago
- A lightweight neural network library for ESP32 and Arduino, enabling on-device training and simple predictions like XOR. Ideal for microc…☆15Jan 5, 2026Updated 9 months ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- A small C library that implements TOTP, compatible with Google Authenticator☆29Jul 26, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 4 months ago
- ☆14Oct 19, 2019Updated 7 years ago
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 9 months ago
- C++ neural networks with Eigen☆14Jan 23, 2016Updated 10 years ago
- ☆11Jul 9, 2025Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year