adamgallas / SpinalDLALinks
[FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic Matrix Engines”
☆21Updated last year
Alternatives and similar repositories for SpinalDLA
Users that are interested in SpinalDLA are comparing it to the libraries listed below
Sorting:
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆23Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆25Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 2 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆34Updated last year
- ☆71Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆31Updated 2 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆23Updated 2 months ago
- C++ code for HLS FPGA implementation of transformer☆19Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆27Updated 2 months ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- ☆29Updated 2 years ago
- ☆37Updated 6 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- ☆27Updated 6 years ago
- AI Chip project☆31Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Template for project1 TPU☆19Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 2 years ago
- ☆72Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago