adamgallas / SpinalDLALinks
☆18Updated last year
Alternatives and similar repositories for SpinalDLA
Users that are interested in SpinalDLA are comparing it to the libraries listed below
Sorting:
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆20Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆27Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- Template for project1 TPU☆19Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated 2 years ago
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- AI Chip project☆32Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- ☆35Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆34Updated 11 months ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- ☆17Updated 4 months ago
- ☆66Updated 6 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆22Updated 2 years ago
- ☆32Updated 3 months ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆20Updated 2 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆13Updated 2 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆18Updated last year
- Hardware accelerator for convolutional neural networks☆53Updated 3 years ago