[FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic Matrix Engines”
☆22May 6, 2024Updated 2 years ago
Alternatives and similar repositories for SpinalDLA
Users that are interested in SpinalDLA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆24Apr 4, 2024Updated 2 years ago
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆25May 9, 2024Updated 2 years ago
- ☆17Mar 8, 2025Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆69Jan 8, 2024Updated 2 years ago
- An out-of-order processor that supports multiple instruction sets.☆22Aug 23, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆36Nov 13, 2025Updated 6 months ago
- ☆27Jan 22, 2023Updated 3 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆17Aug 26, 2024Updated last year
- ☆12Feb 16, 2019Updated 7 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆29Jan 6, 2026Updated 4 months ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆29Mar 3, 2024Updated 2 years ago
- the GPU implementation of bucket based farthest point sampling, achieves 3-4x speedup than the conventional implementation☆23Apr 27, 2026Updated last month
- CNN accelerator implemented with Spinal HDL☆159Jan 29, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆131Aug 27, 2024Updated last year
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- Translate the source code of Veriog version to Spinalhdl version☆10Jul 1, 2021Updated 4 years ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- the CPU implementation of bucket based farthest point sampling, achieves 7-81x speedup than the conventional implementation☆27Sep 17, 2023Updated 2 years ago
- 基于k210的2021电赛F题数字识别☆15Dec 4, 2021Updated 4 years ago
- hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel☆16Nov 15, 2024Updated last year
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 3 months ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆280Apr 1, 2024Updated 2 years ago
- ☆23Feb 15, 2023Updated 3 years ago
- Open source process design kit for 28nm open process☆80Apr 23, 2024Updated 2 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆19Apr 9, 2024Updated 2 years ago
- SpinalHDL Hardware Math Library☆101Jul 12, 2024Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆62Updated this week
- ☆73Feb 16, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Error-free transformations are used to get results with extra accuracy.☆15Updated this week
- Home page for Microsoft Phi-Ground tech-report☆23Sep 8, 2025Updated 8 months ago
- Voice Activity Detector based on MFCC features and DNN model☆29Jul 3, 2023Updated 2 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆24Nov 8, 2024Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Dec 25, 2019Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆73Nov 7, 2024Updated last year