adamgallas / SpinalDLALinks
[FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic Matrix Engines”
☆21Updated last year
Alternatives and similar repositories for SpinalDLA
Users that are interested in SpinalDLA are comparing it to the libraries listed below
Sorting:
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆23Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆25Updated last year
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- A scalable Eyeriss model in SystemC.☆31Updated 2 years ago
- ☆28Updated 6 years ago
- ☆38Updated 6 years ago
- ☆36Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆25Updated 3 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆20Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- Template for project1 TPU☆20Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- ☆36Updated 4 years ago
- ☆18Updated last year
- ☆19Updated 7 months ago
- Open-source of MSD framework☆16Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- ☆59Updated 7 months ago
- ☆71Updated 7 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆28Updated 3 months ago
- ☆12Updated 2 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 2 years ago