meiniKi / FazyRVLinks
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
☆108Updated 2 months ago
Alternatives and similar repositories for FazyRV
Users that are interested in FazyRV are comparing it to the libraries listed below
Sorting:
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆63Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆57Updated this week
- Naive Educational RISC V processor☆90Updated last month
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆80Updated last month
- RISC-V Nox core☆68Updated 3 months ago
- Raptor end-to-end FPGA Compiler and GUI☆90Updated 11 months ago
- ☆71Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆111Updated last year
- A Risc-V SoC for Tiny Tapeout☆43Updated this week
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆85Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated 2 years ago
- A pipelined RISC-V processor☆62Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 5 months ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Spen's Official OpenOCD Mirror☆50Updated 8 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated this week
- ☆60Updated 4 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆185Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated 2 weeks ago