A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
☆124Nov 3, 2026Updated this week
Alternatives and similar repositories for FazyRV
Users that are interested in FazyRV are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Risc-V SoC for Tiny Tapeout☆61Updated this week
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Jun 8, 2023Updated 3 years ago
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 6 months ago
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V RV32E core designed for minimal area☆27Nov 17, 2024Updated last year
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 8 months ago
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Oct 30, 2026Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆112Aug 31, 2026Updated 2 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆231Feb 19, 2026Updated 8 months ago
- A QSPI Pmod board designed in KiCad containing one Flash and two SPRAMs☆16Feb 21, 2026Updated 8 months ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12May 7, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated last month
- Project template for wafer.space MPW runs using the gf180mcu PDK☆60Oct 20, 2026Updated 2 weeks ago
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Apr 16, 2026Updated 6 months ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆45Apr 11, 2024Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆267Updated this week
- [Moved to Codeberg] Another size-optimized RISC-V CPU for your consideration.☆61May 10, 2026Updated 5 months ago
- SAR ADC on tiny tapeout☆55Jan 29, 2025Updated last year
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆151Updated this week
- FLIX-V: FPGA, Linux and RISC-V☆42Nov 5, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instrum…☆64Nov 16, 2025Updated 11 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆871Updated this week
- ASIC implementation flow infrastructure, successor to OpenLane☆624Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆74Jun 28, 2025Updated last year
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆21Jul 25, 2023Updated 3 years ago
- HDL tools layer for OpenEmbedded☆18Oct 20, 2024Updated 2 years ago
- Fabric generator and CAD tools graphical frontend☆19Oct 6, 2026Updated 3 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆176Nov 10, 2025Updated 11 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Topaz Computer☆15Jul 15, 2026Updated 3 months ago
- RISC-V Nox core☆73Jul 22, 2025Updated last year
- A pipelined RISC-V processor☆65Dec 1, 2023Updated 2 years ago
- 3-stage RV32IMACZb* processor with debug☆1,131Aug 29, 2026Updated 2 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆22Sep 30, 2026Updated last month
- ☆42Oct 16, 2026Updated 2 weeks ago
- Custom Standard Cell Library for GF180MCU process node on open PDK.☆14Oct 11, 2026Updated 3 weeks ago