Alternatives and similar repositories for FazyRV:

Users that are interested in FazyRV are comparing it to the libraries listed below

• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆56Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 7 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆53Updated this week
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆74Updated last week
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆73Updated 2 months ago
• olofk / corescore
  CoreScore
  ☆143Updated last month
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆71Updated 11 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• pieter3d / simview
  ☆77Updated last year
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆95Updated 7 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆44Updated last year
• efabless / clear
  ☆66Updated 6 months ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆44Updated 7 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆88Updated 4 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated 2 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆39Updated last month
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆165Updated 11 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆76Updated this week
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 3 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆59Updated 3 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated last month