meiniKi / FazyRVLinks
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
☆95Updated last month
Alternatives and similar repositories for FazyRV
Users that are interested in FazyRV are comparing it to the libraries listed below
Sorting:
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆47Updated last month
- A pipelined RISC-V processor☆57Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- Naive Educational RISC V processor☆84Updated last month
- RISC-V Nox core☆65Updated 3 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last month
- Dual-issue RV64IM processor for fun & learning☆62Updated 2 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆85Updated 3 weeks ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- ☆70Updated 10 months ago
- Raptor end-to-end FPGA Compiler and GUI☆83Updated 7 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Experimental flows using nextpnr for Xilinx devices☆49Updated last month
- Wishbone interconnect utilities☆41Updated 5 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated 11 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Drawio => VHDL and Verilog☆56Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆62Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- ☆79Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- Spen's Official OpenOCD Mirror☆50Updated 4 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆174Updated last year