tomverbeure / mr1Links
MR1 formally verified RISC-V CPU
☆53Updated 6 years ago
Alternatives and similar repositories for mr1
Users that are interested in mr1 are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆73Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆108Updated 2 years ago
- ☆63Updated 6 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 9 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A pipelined RISC-V processor☆57Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆43Updated 2 weeks ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Visual Simulation of Register Transfer Logic☆99Updated 3 months ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 3 weeks ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆58Updated this week
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated 2 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 4 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Yet Another RISC-V Implementation☆93Updated 9 months ago