Chisel implementation of Neural Processing Unit for System on the Chip
☆34May 22, 2026Updated 2 months ago
Alternatives and similar repositories for chisel-npu
Users that are interested in chisel-npu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆261Apr 8, 2024Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- CoralNPU behavior simulator based on MPACT-Sim☆24Jun 10, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆55Jan 2, 2025Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- ☆14Updated this week
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- ☆31Aug 8, 2020Updated 5 years ago
- ☆22Nov 3, 2025Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆179Mar 5, 2025Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆160Feb 24, 2025Updated last year
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆931Jul 8, 2026Updated last week
- ☆15Nov 11, 2015Updated 10 years ago
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated 2 years ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- liberty介绍--LIBERATE工具使用☆18Jul 22, 2019Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆174Jul 25, 2019Updated 6 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 7 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆23Nov 9, 2025Updated 8 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jun 30, 2026Updated 3 weeks ago
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- This is a Project to Integrate and Automate the functions of three tools named gem5, McPAT and HotSpot.☆11Jul 1, 2019Updated 7 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- FPU Generator☆20Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Feb 5, 2026Updated 5 months ago
- ☆19Apr 29, 2025Updated last year
- ☆12Updated this week
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- RISC-V Integrated Matrix Development Repository☆25Jun 29, 2026Updated 3 weeks ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year