Chisel implementation of Neural Processing Unit for System on the Chip
☆34May 22, 2026Updated last month
Alternatives and similar repositories for chisel-npu
Users that are interested in chisel-npu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆256Apr 8, 2024Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- RISC-V Integrated Matrix Development Repository☆25Jun 22, 2026Updated last week
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆56Jan 2, 2025Updated last year
- ☆14Feb 24, 2025Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 8 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆22Nov 3, 2025Updated 7 months ago
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago
- ☆15Nov 11, 2015Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆31Aug 8, 2020Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- liberty介绍--LIBERATE工具使用☆18Jul 22, 2019Updated 6 years ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 6 months ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆175Mar 5, 2025Updated last year
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆922Updated this week
- Open source process design kit for 28nm open process☆84Apr 23, 2024Updated 2 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆175Jul 25, 2019Updated 6 years ago
- SoC Based on ARM Cortex-M3☆39May 16, 2025Updated last year
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jun 21, 2026Updated last week
- ☆12Dec 23, 2025Updated 6 months ago
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆35Jun 1, 2026Updated last month
- DUTH RISC V Microprocessor for High Level Synthesis☆10Jun 23, 2023Updated 3 years ago
- This is a Project to Integrate and Automate the functions of three tools named gem5, McPAT and HotSpot.☆11Jul 1, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39Jun 23, 2026Updated last week
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated last year
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- verilog实现systolic array及配套IO☆14Dec 2, 2024Updated last year