Chisel implementation of Neural Processing Unit for System on the Chip
☆39Oct 15, 2026Updated 2 weeks ago
Alternatives and similar repositories for chisel-npu
Users that are interested in chisel-npu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- npu☆13Sep 5, 2018Updated 8 years ago
- ☆267Apr 8, 2024Updated 2 years ago
- ☆28Jun 21, 2024Updated 2 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- Design a cache by using Verilog☆13Jan 12, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆172Feb 24, 2025Updated last year
- ☆15Apr 24, 2023Updated 3 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Oct 20, 2026Updated last week
- ☆31Aug 8, 2020Updated 6 years ago
- ☆13Jan 24, 2026Updated 9 months ago
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆181Mar 5, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- CNN accelerator implemented with Spinal HDL☆162Sep 29, 2026Updated last month
- RISC-V AI Accelerator SoC with innovative BitNet multiplier-free architecture. Features PicoRV32 CPU, dual AI accelerators (6.4 GOPS), an…☆13Jan 20, 2026Updated 9 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆22Aug 19, 2026Updated 2 months ago
- Theia: ray graphic processing unit☆22Jul 17, 2014Updated 12 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆583Jan 5, 2019Updated 7 years ago
- ☆67May 14, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆970Updated this week
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, A…☆47Nov 8, 2023Updated 2 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- ☆16Jul 16, 2026Updated 3 months ago
- A python-based transactional level model for a Eyeriss as a systolic array☆10Dec 19, 2018Updated 7 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- CoralNPU behavior simulator based on MPACT-Sim☆28Oct 8, 2026Updated 3 weeks ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆179Jul 25, 2019Updated 7 years ago
- 实现带有BD(Buffer Description缓存描述符)的四通道DMA控制器设计,每个通道包括配置寄存器模块,源端控制模 块,缓存模块和目的端控制模块☆12Sep 12, 2023Updated 3 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 4 years ago
- Open-source NPU (Neural Processing Unit) for LLM inference - runs GPT-2, LLaMA, Mistral, Qwen2☆12Mar 15, 2026Updated 7 months ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆241Dec 22, 2025Updated 10 months ago
- Vector processor for RISC-V vector ISA☆147Oct 19, 2020Updated 6 years ago