mpskex / chisel-npuLinks
Chisel implementation of Neural Processing Unit for System on the Chip
☆25Updated 4 months ago
Alternatives and similar repositories for chisel-npu
Users that are interested in chisel-npu are comparing it to the libraries listed below
Sorting:
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆33Updated 2 months ago
- ☆31Updated 5 years ago
- A small Neural Network Processor for Edge devices.☆14Updated 3 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 8 months ago
- ☆40Updated 6 years ago
- ☆57Updated 6 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- ☆33Updated last month
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- ☆15Updated 3 years ago
- ☆61Updated 8 months ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆32Updated 3 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated last week
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆90Updated last week
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- matrix-coprocessor for RISC-V☆26Updated 3 weeks ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆21Updated 3 weeks ago