SpinalHDL / rvlsLinks
RISCV lock-step checker based on Spike
☆12Updated 3 months ago
Alternatives and similar repositories for rvls
Users that are interested in rvls are comparing it to the libraries listed below
Sorting:
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆34Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆13Updated last week
- Branch Predictor Optimization for BlackParrot☆15Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last month
- RISC-V Core Local Interrupt Controller (CLINT)☆27Updated 3 weeks ago
- CMake based hardware build system☆29Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated 3 weeks ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated 2 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 3 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆22Updated 2 weeks ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆24Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆22Updated last month
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆18Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆34Updated last month
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- ☆68Updated this week