bobbl / rudolvLinks
RISC-V processor
☆32Updated 3 years ago
Alternatives and similar repositories for rudolv
Users that are interested in rudolv are comparing it to the libraries listed below
Sorting:
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Demo SoC for SiliconCompiler.☆61Updated 2 weeks ago
- ☆32Updated 2 years ago
- ☆23Updated 5 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- PicoRV☆43Updated 5 years ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- ☆10Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- Open Processor Architecture☆26Updated 9 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- ☆27Updated 8 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆65Updated last week
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆16Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated last month