kiclu / rv6Links
Pipelined 64-bit RISC-V core
☆14Updated last year
Alternatives and similar repositories for rv6
Users that are interested in rv6 are comparing it to the libraries listed below
Sorting:
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆17Updated 3 months ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆24Updated last month
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆12Updated last year
- ☆22Updated 4 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 months ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- 给NEMU移植Linux Kernel!☆18Updated last month
- The official NaplesPU hardware code repository☆17Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆98Updated last week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last month
- ☆22Updated 2 years ago
- Simple UVM environment for experimenting with Verilator.☆22Updated 2 months ago
- Lab assignments for the Agile Hardware Design course☆16Updated last month
- A Rocket-based RISC-V superscalar in-order core☆33Updated 2 months ago
- ☆20Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- An almost empty chisel project as a starting point for hardware design☆32Updated 5 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆27Updated last month
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 6 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- gem5 相关中文笔记☆15Updated 3 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated 3 weeks ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago