kiclu / rv6Links
Pipelined 64-bit RISC-V core
☆14Updated last year
Alternatives and similar repositories for rv6
Users that are interested in rv6 are comparing it to the libraries listed below
Sorting:
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆17Updated 4 months ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Updated 2 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Simple UVM environment for experimenting with Verilator.☆23Updated 3 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last week
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆25Updated 2 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- gem5 相关中文笔记☆15Updated 3 years ago
- ☆22Updated 4 years ago
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆28Updated 2 months ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Updated last year
- A Rocket-based RISC-V superscalar in-order core☆35Updated 3 months ago
- Example of Chisel3 Diplomacy☆11Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last month
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 3 months ago
- An almost empty chisel project as a starting point for hardware design☆32Updated 6 months ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆29Updated 5 years ago
- 给NEMU移植Linux Kernel!☆18Updated 2 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- ☆22Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆39Updated 2 weeks ago
- ☆72Updated last week