ZipCPU / zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
☆43Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for zbasic
- SoftCPU/SoC engine-V☆54Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A reimplementation of a tiny stack CPU☆80Updated 11 months ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- A Verilog Synthesis Regression Test☆34Updated 7 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆73Updated 5 years ago
- LatticeMico32 soft processor☆102Updated 10 years ago
- CMod-S6 SoC☆36Updated 6 years ago
- Demo SoC for SiliconCompiler.☆52Updated last week
- ☆63Updated 5 years ago
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- Tools for FPGA development.☆44Updated last year
- Spen's Official OpenOCD Mirror☆47Updated 8 months ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 9 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- FuseSoC standard core library☆112Updated 3 weeks ago
- Yet Another RISC-V Implementation☆84Updated last month
- A utility for Composing FPGA designs from Peripherals☆168Updated 9 months ago
- Yosys Plugins☆20Updated 5 years ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated last week
- An Open Source configuration of the Arty platform☆122Updated 9 months ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆59Updated last week
- A single-wire bi-directional chip-to-chip interface for FPGAs☆114Updated 8 years ago