A utility for Composing FPGA designs from Peripherals
☆189Jul 1, 2026Updated this week
Alternatives and similar repositories for autofpga
Users that are interested in autofpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Oct 27, 2022Updated 3 years ago
- A wishbone controlled scope for FPGA's☆92Jan 12, 2024Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆43Jan 18, 2024Updated 2 years ago
- Bus bridges and other odds and ends☆683Jun 2, 2026Updated last month
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A small, light weight, RISC CPU soft core☆1,559Dec 8, 2025Updated 6 months ago
- An Open Source configuration of the Arty platform☆132Jan 17, 2024Updated 2 years ago
- A simple, basic, formally verified UART controller☆342Jan 29, 2024Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 7 years ago
- A Python toolbox for building complex digital hardware☆1,328Jan 5, 2026Updated 6 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,429Updated this week
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆11Apr 30, 2023Updated 3 years ago
- Open FPGA tools☆260Mar 30, 2020Updated 6 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Icestudio collection for standard Input-Output in different devices☆15Jun 28, 2024Updated 2 years ago
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 6 years ago
- Small footprint and configurable DRAM core☆520Jun 22, 2026Updated last week
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆687Jan 8, 2022Updated 4 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- An abstraction library for interfacing EDA tools☆774Updated this week
- A Video display simulator☆182May 16, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The original high performance and small footprint system-on-chip based on Migen™☆343Jan 5, 2026Updated 6 months ago
- ☆26Feb 26, 2024Updated 2 years ago
- Build Customized FPGA Implementations for Vivado☆382Jun 27, 2026Updated last week
- VHDL library 4 FPGAs☆186Jun 12, 2026Updated 3 weeks ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆16Feb 22, 2019Updated 7 years ago
- ☆26Feb 15, 2025Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆108Oct 3, 2019Updated 6 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆260Apr 18, 2024Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- nextpnr portable FPGA place and route tool☆1,704Jun 21, 2026Updated 2 weeks ago
- Build your hardware, easily!☆3,969Updated this week
- Small footprint and configurable embedded FPGA logic analyzer☆205Jun 25, 2026Updated last week
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆606Jul 30, 2025Updated 11 months ago
- ☆10Nov 8, 2019Updated 6 years ago
- An Open-source FPGA IP Generator☆1,118Jun 27, 2026Updated last week
- HDL symbol generator☆204Feb 2, 2023Updated 3 years ago