ZipCPU / autofpgaLinks
A utility for Composing FPGA designs from Peripherals
☆185Updated 10 months ago
Alternatives and similar repositories for autofpga
Users that are interested in autofpga are comparing it to the libraries listed below
Sorting:
- An Open Source configuration of the Arty platform☆133Updated last year
- FuseSoC standard core library☆147Updated 4 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ☆137Updated 10 months ago
- Verilog wishbone components☆119Updated last year
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- A wishbone controlled scope for FPGA's☆84Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- A Video display simulator☆173Updated 5 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- VHDL library 4 FPGAs☆181Updated last week
- A single-wire bi-directional chip-to-chip interface for FPGAs☆122Updated 9 years ago
- Basic RISC-V CPU implementation in VHDL.☆169Updated 5 years ago
- Collection of open-source peripherals in Verilog☆183Updated 3 years ago
- ☆112Updated 4 years ago
- Project X-Ray Database: XC7 Series☆71Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆155Updated 7 years ago