ZipCPU / autofpgaLinks
A utility for Composing FPGA designs from Peripherals
☆185Updated 11 months ago
Alternatives and similar repositories for autofpga
Users that are interested in autofpga are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆149Updated 6 months ago
- An Open Source configuration of the Arty platform☆132Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- ☆137Updated 11 months ago
- A Video display simulator☆174Updated 6 months ago
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- A wishbone controlled scope for FPGA's☆84Updated last year
- Xilinx Unisim Library in Verilog☆87Updated 5 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Verilog wishbone components☆123Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- VHDL library 4 FPGAs☆181Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆157Updated 8 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- ☆87Updated last month
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆219Updated 2 weeks ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- Basic RISC-V CPU implementation in VHDL.☆171Updated 5 years ago