bigmagic123 / d1-nezha-baremetaLinks
riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)
☆84Updated 3 years ago
Alternatives and similar repositories for d1-nezha-baremeta
Users that are interested in d1-nezha-baremeta are comparing it to the libraries listed below
Sorting:
- Linux0.11 with MMU for K210(RISC-V) Version☆89Updated 5 years ago
- DEPRECATED: Please update to risc-none-elf-gcc-xpack☆125Updated 2 years ago
- Embedded libc,especially for RISC-V.☆38Updated this week
- ☆35Updated 2 months ago
- K210 run linux nommu (From Damien Le Moal's patch)☆159Updated 2 years ago
- Nuclei RISC-V Software Development Kit☆150Updated this week
- RISC-V port of newlib☆101Updated 3 years ago
- Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC☆107Updated 2 years ago
- The directory to save Bumblebee core's documents, just for GD32VF103 RISC-V Core☆43Updated 4 years ago
- A baremetal experiment of Allwinner D1, without FEL☆33Updated 2 years ago
- The GNU MCU Eclipse RISC-V Embedded GCC☆78Updated 6 years ago
- C-SKY Linux Port☆75Updated 3 weeks ago
- Mainline-friendly SPL for D1☆34Updated 3 years ago
- Allwinner D1 For RISCV-64 Boards Awesome.☆86Updated 3 years ago
- Buildroot for T-HEAD XuanTie CPU Series☆116Updated last year
- Tiny FEL tools for allwinner SOC, support RISC-V D1 chip☆279Updated this week
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆103Updated 7 months ago
- Community's fork of Loongson PMON bootloader☆34Updated last year
- a riscv32 rv32imc emulator written in c.☆33Updated 3 months ago
- Mutil-Operating Syste with RT-Thread☆19Updated 3 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- The demo projects for Allwinner D1 SBC☆24Updated 4 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库!☆15Updated last year
- Buildroot customized for Xuantie™ RISC-V CPU☆47Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Updated 2 years ago
- Testing the speed of CPU and more on generations of hardware.☆50Updated 2 months ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆15Updated 2 years ago
- Nuclei RISC-V Linux Software Development Kit☆54Updated this week
- GNU toolchain for AndesCore☆28Updated 5 months ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago