XUANTIE-RV / xuantie-gnu-toolchain
GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
☆90Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for xuantie-gnu-toolchain
- ☆39Updated 2 years ago
- Linux kernel source tree☆40Updated last month
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆77Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- RISC-V Summit China 2023☆42Updated last year
- ☆10Updated 4 years ago
- RISC-V Nexus Trace TG documentation and reference code☆44Updated 2 months ago
- Nuclei RISC-V Software Development Kit☆125Updated this week
- ☆81Updated this week
- ☆81Updated 2 years ago
- RISC-V Profiles and Platform Specification☆112Updated last year
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆52Updated 11 months ago
- Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.☆31Updated 4 months ago
- Documentation of the RISC-V C API☆75Updated last week
- ☆20Updated this week
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Updated 3 weeks ago
- RISC-V Architecture Profiles☆119Updated 3 weeks ago
- RISC-V Scratchpad☆59Updated 2 years ago
- PLIC Specification☆133Updated last year
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆24Updated 2 years ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆62Updated 3 years ago
- RISC-V IOMMU Specification☆96Updated this week
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆26Updated 3 years ago
- A port of FreeRTOS for the RISC-V ISA☆75Updated 5 years ago
- Trivial RISC-V Linux binary bootloader☆45Updated 3 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 7 months ago
- Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.☆33Updated 7 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆109Updated 3 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆80Updated 2 weeks ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆38Updated 3 months ago