XUANTIE-RV / tvmLinks
TVM for chips base on Xuantie CPU, an open deep learning compiler stack.
☆30Updated last year
Alternatives and similar repositories for tvm
Users that are interested in tvm are comparing it to the libraries listed below
Sorting:
- An optimized neural network operator library for chips base on Xuantie CPU.☆96Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆48Updated last month
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated last month
- Learn NVDLA by SOMNIA☆42Updated 6 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆117Updated 2 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 3 years ago
- ☆49Updated 6 years ago
- ☆42Updated 10 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆49Updated 2 weeks ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- ☆90Updated last month
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 5 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆14Updated 3 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Updated last week
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 6 months ago
- ☆88Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆28Updated 2 weeks ago
- A Heterogeneous GPU Platform for Chipyard SoC☆42Updated this week
- RISC-V Matrix Specification☆23Updated last year
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated last week
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Updated 2 years ago
- ☆33Updated 2 years ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- For CPU experiment☆14Updated 4 years ago