XUANTIE-RV / tvm
TVM for chips base on Xuantie CPU, an open deep learning compiler stack.
☆29Updated 2 months ago
Related projects: ⓘ
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 3 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆93Updated 2 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆32Updated last month
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆80Updated last year
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆39Updated 3 years ago
- ☆27Updated 2 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆48Updated 4 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆83Updated 2 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆57Updated last week
- ☆41Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆15Updated last month
- GPGPU supporting RISCV-V, developed with verilog HDL☆53Updated last month
- Tests for example Rocket Custom Coprocessors☆68Updated 4 years ago
- ☆35Updated 5 years ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- ☆73Updated 11 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆93Updated last year
- ☆42Updated 2 years ago
- ☆21Updated 5 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆52Updated last year
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆22Updated last year
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆36Updated 3 months ago
- ☆71Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆65Updated last month
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆25Updated 8 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆44Updated 7 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆28Updated 6 months ago
- ☆30Updated last year
- cycle accurate Network-on-Chip Simulator☆24Updated last year